1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MSM Display Port Controller 8 9maintainers: 10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 11 - Abhinav Kumar <quic_abhinavk@quicinc.com> 12 13description: | 14 Device tree bindings for DisplayPort host controller for MSM targets 15 that are compatible with VESA DisplayPort interface specification. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - qcom,sa8775p-dp 22 - qcom,sc7180-dp 23 - qcom,sc7280-dp 24 - qcom,sc7280-edp 25 - qcom,sc8180x-dp 26 - qcom,sc8180x-edp 27 - qcom,sc8280xp-dp 28 - qcom,sc8280xp-edp 29 - qcom,sdm845-dp 30 - qcom,sm8350-dp 31 - qcom,sm8650-dp 32 - qcom,x1e80100-dp 33 34 - items: 35 - enum: 36 - qcom,sm6350-dp 37 - const: qcom,sc7180-dp 38 39 # deprecated entry for compatibility with old DT 40 - items: 41 - enum: 42 - qcom,sm6350-dp 43 - const: qcom,sm8350-dp 44 deprecated: true 45 46 - items: 47 - enum: 48 - qcom,sar2130p-dp 49 - qcom,sm7150-dp 50 - qcom,sm8150-dp 51 - qcom,sm8250-dp 52 - qcom,sm8450-dp 53 - qcom,sm8550-dp 54 - const: qcom,sm8350-dp 55 56 - items: 57 - enum: 58 - qcom,sm8750-dp 59 - const: qcom,sm8650-dp 60 61 reg: 62 minItems: 4 63 items: 64 - description: ahb register block 65 - description: aux register block 66 - description: link register block 67 - description: p0 register block 68 - description: p1 register block 69 - description: p2 register block 70 - description: p3 register block 71 - description: mst2link register block 72 - description: mst3link register block 73 74 interrupts: 75 maxItems: 1 76 77 clocks: 78 minItems: 5 79 items: 80 - description: AHB clock to enable register access 81 - description: Display Port AUX clock 82 - description: Display Port Link clock 83 - description: Link interface clock between DP and PHY 84 - description: Display Port stream 0 Pixel clock 85 - description: Display Port stream 1 Pixel clock 86 - description: Display Port stream 2 Pixel clock 87 - description: Display Port stream 3 Pixel clock 88 89 clock-names: 90 minItems: 5 91 items: 92 - const: core_iface 93 - const: core_aux 94 - const: ctrl_link 95 - const: ctrl_link_iface 96 - const: stream_pixel 97 - const: stream_1_pixel 98 - const: stream_2_pixel 99 - const: stream_3_pixel 100 101 phys: 102 maxItems: 1 103 104 phy-names: 105 items: 106 - const: dp 107 108 operating-points-v2: true 109 110 opp-table: 111 type: object 112 113 power-domains: 114 maxItems: 1 115 116 aux-bus: 117 $ref: /schemas/display/dp-aux-bus.yaml# 118 119 data-lanes: 120 $ref: /schemas/types.yaml#/definitions/uint32-array 121 deprecated: true 122 minItems: 1 123 maxItems: 4 124 items: 125 maximum: 3 126 127 "#sound-dai-cells": 128 const: 0 129 130 vdda-0p9-supply: 131 deprecated: true 132 vdda-1p2-supply: 133 deprecated: true 134 135 ports: 136 $ref: /schemas/graph.yaml#/properties/ports 137 properties: 138 port@0: 139 $ref: /schemas/graph.yaml#/properties/port 140 description: Input endpoint of the controller 141 142 port@1: 143 $ref: /schemas/graph.yaml#/$defs/port-base 144 unevaluatedProperties: false 145 description: Output endpoint of the controller 146 properties: 147 endpoint: 148 $ref: /schemas/media/video-interfaces.yaml# 149 unevaluatedProperties: false 150 properties: 151 data-lanes: 152 minItems: 1 153 maxItems: 4 154 items: 155 enum: [ 0, 1, 2, 3 ] 156 157 link-frequencies: 158 minItems: 1 159 maxItems: 4 160 items: 161 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ] 162 163 required: 164 - port@0 165 - port@1 166 167required: 168 - compatible 169 - reg 170 - interrupts 171 - clocks 172 - clock-names 173 - phys 174 - phy-names 175 - power-domains 176 - ports 177 178allOf: 179 # AUX BUS does not exist on DP controllers 180 # Audio output also is present only on DP output 181 - if: 182 properties: 183 compatible: 184 contains: 185 enum: 186 - qcom,sc7280-edp 187 - qcom,sc8180x-edp 188 - qcom,sc8280xp-edp 189 then: 190 properties: 191 "#sound-dai-cells": false 192 else: 193 if: 194 properties: 195 compatible: 196 contains: 197 enum: 198 - qcom,sa8775p-dp 199 - qcom,x1e80100-dp 200 then: 201 oneOf: 202 - required: 203 - aux-bus 204 - required: 205 - "#sound-dai-cells" 206 else: 207 properties: 208 aux-bus: false 209 required: 210 - "#sound-dai-cells" 211 212 - if: 213 properties: 214 compatible: 215 contains: 216 enum: 217 # these platforms support SST only 218 - qcom,sc7180-dp 219 - qcom,sc7280-dp 220 - qcom,sc7280-edp 221 - qcom,sc8180x-edp 222 - qcom,sc8280xp-edp 223 then: 224 properties: 225 reg: 226 minItems: 5 227 maxItems: 5 228 clocks: 229 minItems: 5 230 maxItems: 5 231 clocks-names: 232 minItems: 5 233 maxItems: 5 234 235 - if: 236 properties: 237 compatible: 238 contains: 239 enum: 240 # these platforms support 2 streams MST on some interfaces, 241 # others are SST only 242 - qcom,sc8280xp-dp 243 - qcom,x1e80100-dp 244 then: 245 properties: 246 reg: 247 minItems: 5 248 maxItems: 5 249 clocks: 250 minItems: 5 251 maxItems: 6 252 clocks-names: 253 minItems: 5 254 maxItems: 6 255 256 - if: 257 properties: 258 compatible: 259 contains: 260 # 2 streams MST 261 enum: 262 - qcom,sc8180x-dp 263 - qcom,sdm845-dp 264 - qcom,sm8350-dp 265 - qcom,sm8650-dp 266 then: 267 properties: 268 reg: 269 minItems: 5 270 maxItems: 5 271 clocks: 272 minItems: 6 273 maxItems: 6 274 clocks-names: 275 minItems: 6 276 maxItems: 6 277 278 - if: 279 properties: 280 compatible: 281 contains: 282 enum: 283 # these platforms support 4 stream MST on first DP, 284 # 2 streams MST on the second one. 285 - qcom,sa8775p-dp 286 then: 287 properties: 288 reg: 289 minItems: 9 290 maxItems: 9 291 clocks: 292 minItems: 6 293 maxItems: 8 294 clocks-names: 295 minItems: 6 296 maxItems: 8 297 298additionalProperties: false 299 300examples: 301 - | 302 #include <dt-bindings/interrupt-controller/arm-gic.h> 303 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 304 #include <dt-bindings/power/qcom-rpmpd.h> 305 306 displayport-controller@ae90000 { 307 compatible = "qcom,sc7180-dp"; 308 reg = <0xae90000 0x200>, 309 <0xae90200 0x200>, 310 <0xae90400 0xc00>, 311 <0xae91000 0x400>, 312 <0xae91400 0x400>; 313 interrupt-parent = <&mdss>; 314 interrupts = <12>; 315 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 316 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 317 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 318 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 319 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 320 clock-names = "core_iface", "core_aux", 321 "ctrl_link", 322 "ctrl_link_iface", "stream_pixel"; 323 324 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 325 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 326 327 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 328 329 phys = <&dp_phy>; 330 phy-names = "dp"; 331 332 #sound-dai-cells = <0>; 333 334 power-domains = <&rpmhpd SC7180_CX>; 335 336 ports { 337 #address-cells = <1>; 338 #size-cells = <0>; 339 340 port@0 { 341 reg = <0>; 342 endpoint { 343 remote-endpoint = <&dpu_intf0_out>; 344 }; 345 }; 346 347 port@1 { 348 reg = <1>; 349 endpoint { 350 remote-endpoint = <&typec>; 351 data-lanes = <0 1>; 352 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; 353 }; 354 }; 355 }; 356 }; 357... 358