xref: /linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml (revision 42ac0be18bfa09c03f52244f7c3e15c89b38532f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sc7180-dp
21          - qcom,sc7280-dp
22          - qcom,sc7280-edp
23          - qcom,sc8180x-dp
24          - qcom,sc8180x-edp
25          - qcom,sc8280xp-dp
26          - qcom,sc8280xp-edp
27          - qcom,sdm845-dp
28          - qcom,sm8350-dp
29          - qcom,sm8650-dp
30      - items:
31          - enum:
32              - qcom,sm8150-dp
33              - qcom,sm8250-dp
34              - qcom,sm8450-dp
35              - qcom,sm8550-dp
36          - const: qcom,sm8350-dp
37
38  reg:
39    minItems: 4
40    items:
41      - description: ahb register block
42      - description: aux register block
43      - description: link register block
44      - description: p0 register block
45      - description: p1 register block
46
47  interrupts:
48    maxItems: 1
49
50  clocks:
51    items:
52      - description: AHB clock to enable register access
53      - description: Display Port AUX clock
54      - description: Display Port Link clock
55      - description: Link interface clock between DP and PHY
56      - description: Display Port Pixel clock
57
58  clock-names:
59    items:
60      - const: core_iface
61      - const: core_aux
62      - const: ctrl_link
63      - const: ctrl_link_iface
64      - const: stream_pixel
65
66  assigned-clocks:
67    items:
68      - description: link clock source
69      - description: pixel clock source
70
71  assigned-clock-parents:
72    items:
73      - description: phy 0 parent
74      - description: phy 1 parent
75
76  phys:
77    maxItems: 1
78
79  phy-names:
80    items:
81      - const: dp
82
83  operating-points-v2: true
84
85  opp-table:
86    type: object
87
88  power-domains:
89    maxItems: 1
90
91  aux-bus:
92    $ref: /schemas/display/dp-aux-bus.yaml#
93
94  data-lanes:
95    $ref: /schemas/types.yaml#/definitions/uint32-array
96    deprecated: true
97    minItems: 1
98    maxItems: 4
99    items:
100      maximum: 3
101
102  "#sound-dai-cells":
103    const: 0
104
105  vdda-0p9-supply:
106    deprecated: true
107  vdda-1p2-supply:
108    deprecated: true
109
110  ports:
111    $ref: /schemas/graph.yaml#/properties/ports
112    properties:
113      port@0:
114        $ref: /schemas/graph.yaml#/properties/port
115        description: Input endpoint of the controller
116
117      port@1:
118        $ref: /schemas/graph.yaml#/$defs/port-base
119        unevaluatedProperties: false
120        description: Output endpoint of the controller
121        properties:
122          endpoint:
123            $ref: /schemas/media/video-interfaces.yaml#
124            unevaluatedProperties: false
125            properties:
126              data-lanes:
127                minItems: 1
128                maxItems: 4
129                items:
130                  enum: [ 0, 1, 2, 3 ]
131
132              link-frequencies:
133                minItems: 1
134                maxItems: 4
135                items:
136                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
137
138    required:
139      - port@0
140      - port@1
141
142required:
143  - compatible
144  - reg
145  - interrupts
146  - clocks
147  - clock-names
148  - phys
149  - phy-names
150  - power-domains
151  - ports
152
153allOf:
154  # AUX BUS does not exist on DP controllers
155  # Audio output also is present only on DP output
156  # p1 regions is present on DP, but not on eDP
157  - if:
158      properties:
159        compatible:
160          contains:
161            enum:
162              - qcom,sc7280-edp
163              - qcom,sc8180x-edp
164              - qcom,sc8280xp-edp
165    then:
166      properties:
167        "#sound-dai-cells": false
168    else:
169      properties:
170        aux-bus: false
171        reg:
172          minItems: 5
173      required:
174        - "#sound-dai-cells"
175
176additionalProperties: false
177
178examples:
179  - |
180    #include <dt-bindings/interrupt-controller/arm-gic.h>
181    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
182    #include <dt-bindings/power/qcom-rpmpd.h>
183
184    displayport-controller@ae90000 {
185        compatible = "qcom,sc7180-dp";
186        reg = <0xae90000 0x200>,
187              <0xae90200 0x200>,
188              <0xae90400 0xc00>,
189              <0xae91000 0x400>,
190              <0xae91400 0x400>;
191        interrupt-parent = <&mdss>;
192        interrupts = <12>;
193        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
194                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
195                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
196                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
197                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
198        clock-names = "core_iface", "core_aux",
199                      "ctrl_link",
200                      "ctrl_link_iface", "stream_pixel";
201
202        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
203                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
204
205        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
206
207        phys = <&dp_phy>;
208        phy-names = "dp";
209
210        #sound-dai-cells = <0>;
211
212        power-domains = <&rpmhpd SC7180_CX>;
213
214        ports {
215            #address-cells = <1>;
216            #size-cells = <0>;
217
218            port@0 {
219                reg = <0>;
220                endpoint {
221                    remote-endpoint = <&dpu_intf0_out>;
222                };
223            };
224
225            port@1 {
226                reg = <1>;
227                endpoint {
228                    remote-endpoint = <&typec>;
229                    data-lanes = <0 1>;
230                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
231                };
232            };
233        };
234    };
235...
236