xref: /linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml (revision 0e72db77672ff4758a31fb5259c754a7bb229751) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sc7180-dp
21          - qcom,sc7280-dp
22          - qcom,sc7280-edp
23          - qcom,sc8180x-dp
24          - qcom,sc8180x-edp
25          - qcom,sc8280xp-dp
26          - qcom,sc8280xp-edp
27          - qcom,sdm845-dp
28          - qcom,sm8350-dp
29      - items:
30          - enum:
31              - qcom,sm8250-dp
32              - qcom,sm8450-dp
33              - qcom,sm8550-dp
34          - const: qcom,sm8350-dp
35
36  reg:
37    minItems: 4
38    items:
39      - description: ahb register block
40      - description: aux register block
41      - description: link register block
42      - description: p0 register block
43      - description: p1 register block
44
45  interrupts:
46    maxItems: 1
47
48  clocks:
49    items:
50      - description: AHB clock to enable register access
51      - description: Display Port AUX clock
52      - description: Display Port Link clock
53      - description: Link interface clock between DP and PHY
54      - description: Display Port Pixel clock
55
56  clock-names:
57    items:
58      - const: core_iface
59      - const: core_aux
60      - const: ctrl_link
61      - const: ctrl_link_iface
62      - const: stream_pixel
63
64  assigned-clocks:
65    items:
66      - description: link clock source
67      - description: pixel clock source
68
69  assigned-clock-parents:
70    items:
71      - description: phy 0 parent
72      - description: phy 1 parent
73
74  phys:
75    maxItems: 1
76
77  phy-names:
78    items:
79      - const: dp
80
81  operating-points-v2: true
82
83  opp-table: true
84
85  power-domains:
86    maxItems: 1
87
88  aux-bus:
89    $ref: /schemas/display/dp-aux-bus.yaml#
90
91  data-lanes:
92    $ref: /schemas/types.yaml#/definitions/uint32-array
93    deprecated: true
94    minItems: 1
95    maxItems: 4
96    items:
97      maximum: 3
98
99  "#sound-dai-cells":
100    const: 0
101
102  vdda-0p9-supply:
103    deprecated: true
104  vdda-1p2-supply:
105    deprecated: true
106
107  ports:
108    $ref: /schemas/graph.yaml#/properties/ports
109    properties:
110      port@0:
111        $ref: /schemas/graph.yaml#/properties/port
112        description: Input endpoint of the controller
113
114      port@1:
115        $ref: /schemas/graph.yaml#/$defs/port-base
116        description: Output endpoint of the controller
117        properties:
118          endpoint:
119            $ref: /schemas/media/video-interfaces.yaml#
120            unevaluatedProperties: false
121            properties:
122              data-lanes:
123                minItems: 1
124                maxItems: 4
125                items:
126                  enum: [ 0, 1, 2, 3 ]
127
128              link-frequencies:
129                minItems: 1
130                maxItems: 4
131                items:
132                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
133
134    required:
135      - port@0
136      - port@1
137
138required:
139  - compatible
140  - reg
141  - interrupts
142  - clocks
143  - clock-names
144  - phys
145  - phy-names
146  - power-domains
147  - ports
148
149allOf:
150  # AUX BUS does not exist on DP controllers
151  # Audio output also is present only on DP output
152  # p1 regions is present on DP, but not on eDP
153  - if:
154      properties:
155        compatible:
156          contains:
157            enum:
158              - qcom,sc7280-edp
159              - qcom,sc8180x-edp
160              - qcom,sc8280xp-edp
161    then:
162      properties:
163        "#sound-dai-cells": false
164    else:
165      properties:
166        aux-bus: false
167        reg:
168          minItems: 5
169      required:
170        - "#sound-dai-cells"
171
172additionalProperties: false
173
174examples:
175  - |
176    #include <dt-bindings/interrupt-controller/arm-gic.h>
177    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
178    #include <dt-bindings/power/qcom-rpmpd.h>
179
180    displayport-controller@ae90000 {
181        compatible = "qcom,sc7180-dp";
182        reg = <0xae90000 0x200>,
183              <0xae90200 0x200>,
184              <0xae90400 0xc00>,
185              <0xae91000 0x400>,
186              <0xae91400 0x400>;
187        interrupt-parent = <&mdss>;
188        interrupts = <12>;
189        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
190                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
191                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
192                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
193                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
194        clock-names = "core_iface", "core_aux",
195                      "ctrl_link",
196                      "ctrl_link_iface", "stream_pixel";
197
198        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
199                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
200
201        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
202
203        phys = <&dp_phy>;
204        phy-names = "dp";
205
206        #sound-dai-cells = <0>;
207
208        power-domains = <&rpmhpd SC7180_CX>;
209
210        ports {
211            #address-cells = <1>;
212            #size-cells = <0>;
213
214            port@0 {
215                reg = <0>;
216                endpoint {
217                    remote-endpoint = <&dpu_intf0_out>;
218                };
219            };
220
221            port@1 {
222                reg = <1>;
223                endpoint {
224                    remote-endpoint = <&typec>;
225                    data-lanes = <0 1>;
226                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
227                };
228            };
229        };
230    };
231...
232