xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display UFOe
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display UFOe stands for Unified Frame Optimization engine.
15  UFOe can cut the data rate for DSI port which may lead to reduce power
16  consumption.
17  UFOe device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt8173-disp-ufoe
27      - items:
28          - const: mediatek,mt6795-disp-ufoe
29          - const: mediatek,mt8173-disp-ufoe
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  power-domains:
38    description: A phandle and PM domain specifier as defined by bindings of
39      the power controller specified by phandle. See
40      Documentation/devicetree/bindings/power/power-domain.yaml for details.
41
42  clocks:
43    items:
44      - description: UFOe Clock
45
46  ports:
47    $ref: /schemas/graph.yaml#/properties/ports
48    description:
49      Input and output ports can have multiple endpoints, each of those
50      connects to either the primary, secondary, etc, display pipeline.
51
52    properties:
53      port@0:
54        $ref: /schemas/graph.yaml#/properties/port
55        description: UFOE input, usually from one of the RDMA blocks.
56
57      port@1:
58        $ref: /schemas/graph.yaml#/properties/port
59        description:
60          UFOE output to the input of the next desired component in the
61          display pipeline, usually one of the available DSI blocks.
62
63    required:
64      - port@0
65      - port@1
66
67required:
68  - compatible
69  - reg
70  - interrupts
71  - power-domains
72  - clocks
73
74additionalProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/interrupt-controller/arm-gic.h>
79    #include <dt-bindings/clock/mt8173-clk.h>
80    #include <dt-bindings/power/mt8173-power.h>
81    soc {
82        #address-cells = <2>;
83        #size-cells = <2>;
84
85        ufoe@1401a000 {
86            compatible = "mediatek,mt8173-disp-ufoe";
87            reg = <0 0x1401a000 0 0x1000>;
88            interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
89            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
90            clocks = <&mmsys CLK_MM_DISP_UFOE>;
91        };
92    };
93