xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml (revision c771600c6af14749609b49565ffb4cac2959710d)
14ed545e7Sjason-jh.lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
24ed545e7Sjason-jh.lin%YAML 1.2
34ed545e7Sjason-jh.lin---
44ed545e7Sjason-jh.lin$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
54ed545e7Sjason-jh.lin$schema: http://devicetree.org/meta-schemas/core.yaml#
64ed545e7Sjason-jh.lin
74ed545e7Sjason-jh.lintitle: Mediatek display UFOe
84ed545e7Sjason-jh.lin
94ed545e7Sjason-jh.linmaintainers:
104ed545e7Sjason-jh.lin  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
114ed545e7Sjason-jh.lin  - Philipp Zabel <p.zabel@pengutronix.de>
124ed545e7Sjason-jh.lin
134ed545e7Sjason-jh.lindescription: |
144ed545e7Sjason-jh.lin  Mediatek display UFOe stands for Unified Frame Optimization engine.
154ed545e7Sjason-jh.lin  UFOe can cut the data rate for DSI port which may lead to reduce power
164ed545e7Sjason-jh.lin  consumption.
174ed545e7Sjason-jh.lin  UFOe device node must be siblings to the central MMSYS_CONFIG node.
184ed545e7Sjason-jh.lin  For a description of the MMSYS_CONFIG binding, see
194ed545e7Sjason-jh.lin  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
204ed545e7Sjason-jh.lin  for details.
214ed545e7Sjason-jh.lin
224ed545e7Sjason-jh.linproperties:
234ed545e7Sjason-jh.lin  compatible:
244ed545e7Sjason-jh.lin    oneOf:
25112d5560SKrzysztof Kozlowski      - enum:
26112d5560SKrzysztof Kozlowski          - mediatek,mt8173-disp-ufoe
27c769ecceSAngeloGioacchino Del Regno      - items:
28c769ecceSAngeloGioacchino Del Regno          - const: mediatek,mt6795-disp-ufoe
29c769ecceSAngeloGioacchino Del Regno          - const: mediatek,mt8173-disp-ufoe
304ed545e7Sjason-jh.lin
314ed545e7Sjason-jh.lin  reg:
324ed545e7Sjason-jh.lin    maxItems: 1
334ed545e7Sjason-jh.lin
344ed545e7Sjason-jh.lin  interrupts:
354ed545e7Sjason-jh.lin    maxItems: 1
364ed545e7Sjason-jh.lin
374ed545e7Sjason-jh.lin  power-domains:
384ed545e7Sjason-jh.lin    description: A phandle and PM domain specifier as defined by bindings of
394ed545e7Sjason-jh.lin      the power controller specified by phandle. See
404ed545e7Sjason-jh.lin      Documentation/devicetree/bindings/power/power-domain.yaml for details.
414ed545e7Sjason-jh.lin
424ed545e7Sjason-jh.lin  clocks:
434ed545e7Sjason-jh.lin    items:
444ed545e7Sjason-jh.lin      - description: UFOe Clock
454ed545e7Sjason-jh.lin
46*2b6433f3SAngeloGioacchino Del Regno  ports:
47*2b6433f3SAngeloGioacchino Del Regno    $ref: /schemas/graph.yaml#/properties/ports
48*2b6433f3SAngeloGioacchino Del Regno    description:
49*2b6433f3SAngeloGioacchino Del Regno      Input and output ports can have multiple endpoints, each of those
50*2b6433f3SAngeloGioacchino Del Regno      connects to either the primary, secondary, etc, display pipeline.
51*2b6433f3SAngeloGioacchino Del Regno
52*2b6433f3SAngeloGioacchino Del Regno    properties:
53*2b6433f3SAngeloGioacchino Del Regno      port@0:
54*2b6433f3SAngeloGioacchino Del Regno        $ref: /schemas/graph.yaml#/properties/port
55*2b6433f3SAngeloGioacchino Del Regno        description: UFOE input, usually from one of the RDMA blocks.
56*2b6433f3SAngeloGioacchino Del Regno
57*2b6433f3SAngeloGioacchino Del Regno      port@1:
58*2b6433f3SAngeloGioacchino Del Regno        $ref: /schemas/graph.yaml#/properties/port
59*2b6433f3SAngeloGioacchino Del Regno        description:
60*2b6433f3SAngeloGioacchino Del Regno          UFOE output to the input of the next desired component in the
61*2b6433f3SAngeloGioacchino Del Regno          display pipeline, usually one of the available DSI blocks.
62*2b6433f3SAngeloGioacchino Del Regno
63*2b6433f3SAngeloGioacchino Del Regno    required:
64*2b6433f3SAngeloGioacchino Del Regno      - port@0
65*2b6433f3SAngeloGioacchino Del Regno      - port@1
66*2b6433f3SAngeloGioacchino Del Regno
674ed545e7Sjason-jh.linrequired:
684ed545e7Sjason-jh.lin  - compatible
694ed545e7Sjason-jh.lin  - reg
704ed545e7Sjason-jh.lin  - interrupts
714ed545e7Sjason-jh.lin  - power-domains
724ed545e7Sjason-jh.lin  - clocks
734ed545e7Sjason-jh.lin
744ed545e7Sjason-jh.linadditionalProperties: false
754ed545e7Sjason-jh.lin
764ed545e7Sjason-jh.linexamples:
774ed545e7Sjason-jh.lin  - |
78bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/interrupt-controller/arm-gic.h>
79bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/clock/mt8173-clk.h>
80bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/power/mt8173-power.h>
81bff4e302SAngeloGioacchino Del Regno    soc {
82bff4e302SAngeloGioacchino Del Regno        #address-cells = <2>;
83bff4e302SAngeloGioacchino Del Regno        #size-cells = <2>;
844ed545e7Sjason-jh.lin
854ed545e7Sjason-jh.lin        ufoe@1401a000 {
864ed545e7Sjason-jh.lin            compatible = "mediatek,mt8173-disp-ufoe";
874ed545e7Sjason-jh.lin            reg = <0 0x1401a000 0 0x1000>;
884ed545e7Sjason-jh.lin            interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
894ed545e7Sjason-jh.lin            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
904ed545e7Sjason-jh.lin            clocks = <&mmsys CLK_MM_DISP_UFOE>;
914ed545e7Sjason-jh.lin        };
92bff4e302SAngeloGioacchino Del Regno    };
93