xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml (revision e7d759f31ca295d589f7420719c311870bb3166f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display split
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display split, namely SPLIT, is used to split stream to two
15  encoders.
16  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-split
26          - mediatek,mt8195-mdp3-split
27      - items:
28          - const: mediatek,mt6795-disp-split
29          - const: mediatek,mt8173-disp-split
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  power-domains:
38    description: A phandle and PM domain specifier as defined by bindings of
39      the power controller specified by phandle. See
40      Documentation/devicetree/bindings/power/power-domain.yaml for details.
41
42  mediatek,gce-client-reg:
43    description:
44      The register of display function block to be set by gce. There are 4 arguments,
45      such as gce node, subsys id, offset and register size. The subsys id that is
46      mapping to the register of display function blocks is defined in the gce header
47      include/dt-bindings/gce/<chip>-gce.h of each chips.
48    $ref: /schemas/types.yaml#/definitions/phandle-array
49    items:
50      items:
51        - description: phandle of GCE
52        - description: GCE subsys id
53        - description: register offset
54        - description: register size
55    maxItems: 1
56
57  clocks:
58    items:
59      - description: SPLIT Clock
60
61required:
62  - compatible
63  - reg
64  - power-domains
65  - clocks
66
67allOf:
68  - if:
69      properties:
70        compatible:
71          contains:
72            const: mediatek,mt8195-mdp3-split
73
74    then:
75      required:
76        - mediatek,gce-client-reg
77
78additionalProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/clock/mt8173-clk.h>
83    #include <dt-bindings/power/mt8173-power.h>
84
85    soc {
86        #address-cells = <2>;
87        #size-cells = <2>;
88
89        split0: split@14018000 {
90            compatible = "mediatek,mt8173-disp-split";
91            reg = <0 0x14018000 0 0x1000>;
92            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
93            clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
94        };
95    };
96