xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Read Direct Memory Access
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek Read Direct Memory Access(RDMA) component used to read the
15  data into DMA. It provides real time data to the back-end panel
16  driver, such as DSI, DPI and DP_INTF.
17  It contains one line buffer to store the sufficient pixel data.
18  RDMA device node must be siblings to the central MMSYS_CONFIG node.
19  For a description of the MMSYS_CONFIG binding, see
20  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
21  for details.
22
23properties:
24  compatible:
25    oneOf:
26      - enum:
27          - mediatek,mt2701-disp-rdma
28          - mediatek,mt8173-disp-rdma
29          - mediatek,mt8183-disp-rdma
30          - mediatek,mt8195-disp-rdma
31      - items:
32          - enum:
33              - mediatek,mt8188-disp-rdma
34          - const: mediatek,mt8195-disp-rdma
35      - items:
36          - enum:
37              - mediatek,mt7623-disp-rdma
38              - mediatek,mt2712-disp-rdma
39              - mediatek,mt8167-disp-rdma
40          - const: mediatek,mt2701-disp-rdma
41      - items:
42          - enum:
43              - mediatek,mt6795-disp-rdma
44          - const: mediatek,mt8173-disp-rdma
45      - items:
46          - enum:
47              - mediatek,mt8186-disp-rdma
48              - mediatek,mt8192-disp-rdma
49              - mediatek,mt8365-disp-rdma
50          - const: mediatek,mt8183-disp-rdma
51
52  reg:
53    maxItems: 1
54
55  interrupts:
56    maxItems: 1
57
58  power-domains:
59    description: A phandle and PM domain specifier as defined by bindings of
60      the power controller specified by phandle. See
61      Documentation/devicetree/bindings/power/power-domain.yaml for details.
62
63  clocks:
64    items:
65      - description: RDMA Clock
66
67  iommus:
68    description:
69      This property should point to the respective IOMMU block with master port as argument,
70      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
71
72  mediatek,rdma-fifo-size:
73    description:
74      rdma fifo size may be different even in same SOC, add this property to the
75      corresponding rdma.
76      The value below is the Max value which defined in hardware data sheet
77      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
78      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
79      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
80    $ref: /schemas/types.yaml#/definitions/uint32
81    enum: [8192, 5120, 2048]
82
83  mediatek,gce-client-reg:
84    description: The register of client driver can be configured by gce with
85      4 arguments defined in this property, such as phandle of gce, subsys id,
86      register offset and size. Each GCE subsys id is mapping to a client
87      defined in the header include/dt-bindings/gce/<chip>-gce.h.
88    $ref: /schemas/types.yaml#/definitions/phandle-array
89    maxItems: 1
90
91  ports:
92    $ref: /schemas/graph.yaml#/properties/ports
93    description:
94      Input and output ports can have multiple endpoints, each of those
95      connects to either the primary, secondary, etc, display pipeline.
96
97    properties:
98      port@0:
99        $ref: /schemas/graph.yaml#/properties/port
100        description: RDMA input port, usually from MMSYS, OD or OVL
101
102      port@1:
103        $ref: /schemas/graph.yaml#/properties/port
104        description:
105          RDMA output to the input of the next desired component in the
106          display pipeline, for example one of the available COLOR, DPI,
107          DSI, MERGE or UFOE blocks.
108
109    required:
110      - port@0
111      - port@1
112
113required:
114  - compatible
115  - reg
116  - interrupts
117  - power-domains
118  - clocks
119  - iommus
120
121additionalProperties: false
122
123examples:
124  - |
125    #include <dt-bindings/interrupt-controller/arm-gic.h>
126    #include <dt-bindings/clock/mt8173-clk.h>
127    #include <dt-bindings/power/mt8173-power.h>
128    #include <dt-bindings/gce/mt8173-gce.h>
129    #include <dt-bindings/memory/mt8173-larb-port.h>
130
131    soc {
132        #address-cells = <2>;
133        #size-cells = <2>;
134
135        rdma0: rdma@1400e000 {
136            compatible = "mediatek,mt8173-disp-rdma";
137            reg = <0 0x1400e000 0 0x1000>;
138            interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
139            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
140            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
141            iommus = <&iommu M4U_PORT_DISP_RDMA0>;
142            mediatek,rdma-fifo-size = <8192>;
143            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
144        };
145    };
146