xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Read Direct Memory Access
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek Read Direct Memory Access(RDMA) component used to read the
15  data into DMA. It provides real time data to the back-end panel
16  driver, such as DSI, DPI and DP_INTF.
17  It contains one line buffer to store the sufficient pixel data.
18  RDMA device node must be siblings to the central MMSYS_CONFIG node.
19  For a description of the MMSYS_CONFIG binding, see
20  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
21  for details.
22
23properties:
24  compatible:
25    oneOf:
26      - enum:
27          - mediatek,mt2701-disp-rdma
28          - mediatek,mt8173-disp-rdma
29          - mediatek,mt8183-disp-rdma
30          - mediatek,mt8195-disp-rdma
31      - items:
32          - enum:
33              - mediatek,mt8188-disp-rdma
34          - const: mediatek,mt8195-disp-rdma
35      - items:
36          - enum:
37              - mediatek,mt7623-disp-rdma
38              - mediatek,mt2712-disp-rdma
39              - mediatek,mt8167-disp-rdma
40          - const: mediatek,mt2701-disp-rdma
41      - items:
42          - enum:
43              - mediatek,mt6795-disp-rdma
44          - const: mediatek,mt8173-disp-rdma
45      - items:
46          - enum:
47              - mediatek,mt8186-disp-rdma
48              - mediatek,mt8192-disp-rdma
49              - mediatek,mt8365-disp-rdma
50          - const: mediatek,mt8183-disp-rdma
51
52  reg:
53    maxItems: 1
54
55  interrupts:
56    maxItems: 1
57
58  power-domains:
59    description: A phandle and PM domain specifier as defined by bindings of
60      the power controller specified by phandle. See
61      Documentation/devicetree/bindings/power/power-domain.yaml for details.
62
63  clocks:
64    items:
65      - description: RDMA Clock
66
67  iommus:
68    maxItems: 1
69
70  mediatek,rdma-fifo-size:
71    description:
72      rdma fifo size may be different even in same SOC, add this property to the
73      corresponding rdma.
74      The value below is the Max value which defined in hardware data sheet
75      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
76      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
77      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
78    $ref: /schemas/types.yaml#/definitions/uint32
79    enum: [8192, 5120, 2048]
80
81  mediatek,gce-client-reg:
82    description: The register of client driver can be configured by gce with
83      4 arguments defined in this property, such as phandle of gce, subsys id,
84      register offset and size. Each GCE subsys id is mapping to a client
85      defined in the header include/dt-bindings/gce/<chip>-gce.h.
86    $ref: /schemas/types.yaml#/definitions/phandle-array
87    maxItems: 1
88
89  ports:
90    $ref: /schemas/graph.yaml#/properties/ports
91    description:
92      Input and output ports can have multiple endpoints, each of those
93      connects to either the primary, secondary, etc, display pipeline.
94
95    properties:
96      port@0:
97        $ref: /schemas/graph.yaml#/properties/port
98        description: RDMA input port, usually from MMSYS, OD or OVL
99
100      port@1:
101        $ref: /schemas/graph.yaml#/properties/port
102        description:
103          RDMA output to the input of the next desired component in the
104          display pipeline, for example one of the available COLOR, DPI,
105          DSI, MERGE or UFOE blocks.
106
107    required:
108      - port@0
109      - port@1
110
111required:
112  - compatible
113  - reg
114  - interrupts
115  - power-domains
116  - clocks
117  - iommus
118
119additionalProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/interrupt-controller/arm-gic.h>
124    #include <dt-bindings/clock/mt8173-clk.h>
125    #include <dt-bindings/power/mt8173-power.h>
126    #include <dt-bindings/gce/mt8173-gce.h>
127    #include <dt-bindings/memory/mt8173-larb-port.h>
128
129    soc {
130        #address-cells = <2>;
131        #size-cells = <2>;
132
133        rdma0: rdma@1400e000 {
134            compatible = "mediatek,mt8173-disp-rdma";
135            reg = <0 0x1400e000 0 0x1000>;
136            interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
137            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
138            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
139            iommus = <&iommu M4U_PORT_DISP_RDMA0>;
140            mediatek,rdma-fifo-size = <8192>;
141            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
142        };
143    };
144