xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay, namely OVL, can do alpha blending from
15  the memory.
16  OVL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt2701-disp-ovl
26          - mediatek,mt8167-disp-ovl
27          - mediatek,mt8173-disp-ovl
28          - mediatek,mt8183-disp-ovl
29          - mediatek,mt8192-disp-ovl
30          - mediatek,mt8195-disp-ovl
31          - mediatek,mt8195-mdp3-ovl
32      - items:
33          - enum:
34              - mediatek,mt7623-disp-ovl
35              - mediatek,mt2712-disp-ovl
36          - const: mediatek,mt2701-disp-ovl
37      - items:
38          - enum:
39              - mediatek,mt6795-disp-ovl
40          - const: mediatek,mt8173-disp-ovl
41      - items:
42          - enum:
43              - mediatek,mt8186-disp-ovl
44              - mediatek,mt8365-disp-ovl
45          - const: mediatek,mt8192-disp-ovl
46      - items:
47          - const: mediatek,mt8188-disp-ovl
48          - const: mediatek,mt8195-disp-ovl
49      - items:
50          - const: mediatek,mt8188-mdp3-ovl
51          - const: mediatek,mt8195-mdp3-ovl
52
53  reg:
54    maxItems: 1
55
56  interrupts:
57    maxItems: 1
58
59  power-domains:
60    description: A phandle and PM domain specifier as defined by bindings of
61      the power controller specified by phandle. See
62      Documentation/devicetree/bindings/power/power-domain.yaml for details.
63
64  clocks:
65    items:
66      - description: OVL Clock
67
68  iommus:
69    description:
70      This property should point to the respective IOMMU block with master port as argument,
71      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
72
73  mediatek,gce-client-reg:
74    description: The register of client driver can be configured by gce with
75      4 arguments defined in this property, such as phandle of gce, subsys id,
76      register offset and size. Each GCE subsys id is mapping to a client
77      defined in the header include/dt-bindings/gce/<chip>-gce.h.
78    $ref: /schemas/types.yaml#/definitions/phandle-array
79    maxItems: 1
80
81  ports:
82    $ref: /schemas/graph.yaml#/properties/ports
83    description:
84      Input and output ports can have multiple endpoints, each of those
85      connects to either the primary, secondary, etc, display pipeline.
86
87    properties:
88      port@0:
89        $ref: /schemas/graph.yaml#/properties/port
90        description: OVL input port from MMSYS or one of multiple VDOSYS
91
92      port@1:
93        $ref: /schemas/graph.yaml#/properties/port
94        description:
95          OVL output to the input of the next desired component in the
96          display pipeline, for example one of the available COLOR, RDMA
97          or WDMA blocks.
98
99    required:
100      - port@0
101      - port@1
102
103required:
104  - compatible
105  - reg
106  - interrupts
107  - power-domains
108  - clocks
109  - iommus
110
111additionalProperties: false
112
113examples:
114  - |
115    #include <dt-bindings/interrupt-controller/arm-gic.h>
116    #include <dt-bindings/clock/mt8173-clk.h>
117    #include <dt-bindings/power/mt8173-power.h>
118    #include <dt-bindings/gce/mt8173-gce.h>
119    #include <dt-bindings/memory/mt8173-larb-port.h>
120
121    soc {
122        #address-cells = <2>;
123        #size-cells = <2>;
124
125        ovl0: ovl@1400c000 {
126            compatible = "mediatek,mt8173-disp-ovl";
127            reg = <0 0x1400c000 0 0x1000>;
128            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
129            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
130            clocks = <&mmsys CLK_MM_DISP_OVL0>;
131            iommus = <&iommu M4U_PORT_DISP_OVL0>;
132            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
133        };
134    };
135