xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml (revision eed4edda910fe34dfae8c6bfbcf57f4593a54295) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay, namely OVL, can do alpha blending from
15  the memory.
16  OVL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt2701-disp-ovl
26          - mediatek,mt8173-disp-ovl
27          - mediatek,mt8183-disp-ovl
28          - mediatek,mt8192-disp-ovl
29          - mediatek,mt8195-mdp3-ovl
30      - items:
31          - enum:
32              - mediatek,mt7623-disp-ovl
33              - mediatek,mt2712-disp-ovl
34          - const: mediatek,mt2701-disp-ovl
35      - items:
36          - enum:
37              - mediatek,mt6795-disp-ovl
38          - const: mediatek,mt8173-disp-ovl
39      - items:
40          - enum:
41              - mediatek,mt8188-disp-ovl
42              - mediatek,mt8195-disp-ovl
43          - const: mediatek,mt8183-disp-ovl
44      - items:
45          - enum:
46              - mediatek,mt8186-disp-ovl
47          - const: mediatek,mt8192-disp-ovl
48
49  reg:
50    maxItems: 1
51
52  interrupts:
53    maxItems: 1
54
55  power-domains:
56    description: A phandle and PM domain specifier as defined by bindings of
57      the power controller specified by phandle. See
58      Documentation/devicetree/bindings/power/power-domain.yaml for details.
59
60  clocks:
61    items:
62      - description: OVL Clock
63
64  iommus:
65    description:
66      This property should point to the respective IOMMU block with master port as argument,
67      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
68
69  mediatek,gce-client-reg:
70    description: The register of client driver can be configured by gce with
71      4 arguments defined in this property, such as phandle of gce, subsys id,
72      register offset and size. Each GCE subsys id is mapping to a client
73      defined in the header include/dt-bindings/gce/<chip>-gce.h.
74    $ref: /schemas/types.yaml#/definitions/phandle-array
75    maxItems: 1
76
77required:
78  - compatible
79  - reg
80  - interrupts
81  - power-domains
82  - clocks
83  - iommus
84
85additionalProperties: false
86
87examples:
88  - |
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    #include <dt-bindings/clock/mt8173-clk.h>
91    #include <dt-bindings/power/mt8173-power.h>
92    #include <dt-bindings/gce/mt8173-gce.h>
93    #include <dt-bindings/memory/mt8173-larb-port.h>
94
95    soc {
96        #address-cells = <2>;
97        #size-cells = <2>;
98
99        ovl0: ovl@1400c000 {
100            compatible = "mediatek,mt8173-disp-ovl";
101            reg = <0 0x1400c000 0 0x1000>;
102            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
103            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
104            clocks = <&mmsys CLK_MM_DISP_OVL0>;
105            iommus = <&iommu M4U_PORT_DISP_OVL0>;
106            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
107        };
108    };
109