xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay, namely OVL, can do alpha blending from
15  the memory.
16  OVL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt2701-disp-ovl
26          - mediatek,mt8173-disp-ovl
27          - mediatek,mt8183-disp-ovl
28          - mediatek,mt8192-disp-ovl
29          - mediatek,mt8195-mdp3-ovl
30      - items:
31          - enum:
32              - mediatek,mt7623-disp-ovl
33              - mediatek,mt2712-disp-ovl
34          - const: mediatek,mt2701-disp-ovl
35      - items:
36          - enum:
37              - mediatek,mt6795-disp-ovl
38          - const: mediatek,mt8173-disp-ovl
39      - items:
40          - enum:
41              - mediatek,mt8188-disp-ovl
42              - mediatek,mt8195-disp-ovl
43          - const: mediatek,mt8183-disp-ovl
44      - items:
45          - enum:
46              - mediatek,mt8186-disp-ovl
47              - mediatek,mt8365-disp-ovl
48          - const: mediatek,mt8192-disp-ovl
49
50  reg:
51    maxItems: 1
52
53  interrupts:
54    maxItems: 1
55
56  power-domains:
57    description: A phandle and PM domain specifier as defined by bindings of
58      the power controller specified by phandle. See
59      Documentation/devicetree/bindings/power/power-domain.yaml for details.
60
61  clocks:
62    items:
63      - description: OVL Clock
64
65  iommus:
66    description:
67      This property should point to the respective IOMMU block with master port as argument,
68      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
69
70  mediatek,gce-client-reg:
71    description: The register of client driver can be configured by gce with
72      4 arguments defined in this property, such as phandle of gce, subsys id,
73      register offset and size. Each GCE subsys id is mapping to a client
74      defined in the header include/dt-bindings/gce/<chip>-gce.h.
75    $ref: /schemas/types.yaml#/definitions/phandle-array
76    maxItems: 1
77
78  ports:
79    $ref: /schemas/graph.yaml#/properties/ports
80    description:
81      Input and output ports can have multiple endpoints, each of those
82      connects to either the primary, secondary, etc, display pipeline.
83
84    properties:
85      port@0:
86        $ref: /schemas/graph.yaml#/properties/port
87        description: OVL input port from MMSYS or one of multiple VDOSYS
88
89      port@1:
90        $ref: /schemas/graph.yaml#/properties/port
91        description:
92          OVL output to the input of the next desired component in the
93          display pipeline, for example one of the available COLOR, RDMA
94          or WDMA blocks.
95
96    required:
97      - port@0
98      - port@1
99
100required:
101  - compatible
102  - reg
103  - interrupts
104  - power-domains
105  - clocks
106  - iommus
107
108additionalProperties: false
109
110examples:
111  - |
112    #include <dt-bindings/interrupt-controller/arm-gic.h>
113    #include <dt-bindings/clock/mt8173-clk.h>
114    #include <dt-bindings/power/mt8173-power.h>
115    #include <dt-bindings/gce/mt8173-gce.h>
116    #include <dt-bindings/memory/mt8173-larb-port.h>
117
118    soc {
119        #address-cells = <2>;
120        #size-cells = <2>;
121
122        ovl0: ovl@1400c000 {
123            compatible = "mediatek,mt8173-disp-ovl";
124            reg = <0 0x1400c000 0 0x1000>;
125            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
126            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
127            clocks = <&mmsys CLK_MM_DISP_OVL0>;
128            iommus = <&iommu M4U_PORT_DISP_OVL0>;
129            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
130        };
131    };
132