xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay 2 layer
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
15  for OVL.
16  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8183-disp-ovl-2l
26          - mediatek,mt8192-disp-ovl-2l
27      - items:
28          - enum:
29              - mediatek,mt8186-disp-ovl-2l
30          - const: mediatek,mt8192-disp-ovl-2l
31
32  reg:
33    maxItems: 1
34
35  interrupts:
36    maxItems: 1
37
38  power-domains:
39    description: A phandle and PM domain specifier as defined by bindings of
40      the power controller specified by phandle. See
41      Documentation/devicetree/bindings/power/power-domain.yaml for details.
42
43  clocks:
44    items:
45      - description: OVL-2L Clock
46
47  iommus:
48    description:
49      This property should point to the respective IOMMU block with master port as argument,
50      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
51
52  mediatek,gce-client-reg:
53    description: The register of client driver can be configured by gce with
54      4 arguments defined in this property, such as phandle of gce, subsys id,
55      register offset and size. Each GCE subsys id is mapping to a client
56      defined in the header include/dt-bindings/gce/<chip>-gce.h.
57    $ref: /schemas/types.yaml#/definitions/phandle-array
58    maxItems: 1
59
60  ports:
61    $ref: /schemas/graph.yaml#/properties/ports
62    description:
63      Input and output ports can have multiple endpoints, each of those
64      connects to either the primary, secondary, etc, display pipeline.
65
66    properties:
67      port@0:
68        $ref: /schemas/graph.yaml#/properties/port
69        description: OVL input port from MMSYS, VDOSYS or other OVLs
70
71      port@1:
72        $ref: /schemas/graph.yaml#/properties/port
73        description:
74          OVL output to the input of the next desired component in the
75          display pipeline, for example one of the available COLOR, RDMA
76          or WDMA blocks.
77
78    required:
79      - port@0
80      - port@1
81
82required:
83  - compatible
84  - reg
85  - interrupts
86  - power-domains
87  - clocks
88  - iommus
89
90additionalProperties: false
91
92examples:
93  - |
94    #include <dt-bindings/interrupt-controller/arm-gic.h>
95    #include <dt-bindings/clock/mt8183-clk.h>
96    #include <dt-bindings/power/mt8183-power.h>
97    #include <dt-bindings/gce/mt8183-gce.h>
98    #include <dt-bindings/memory/mt8183-larb-port.h>
99
100    soc {
101        #address-cells = <2>;
102        #size-cells = <2>;
103
104        ovl_2l0: ovl@14009000 {
105            compatible = "mediatek,mt8183-disp-ovl-2l";
106            reg = <0 0x14009000 0 0x1000>;
107            interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
108            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
109            clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
110            iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
111            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
112        };
113    };
114