xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml (revision 0a94608f0f7de9b1135ffea3546afe68eafef57f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay 2 layer
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
15  for OVL.
16  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt8183-disp-ovl-2l
26      - items:
27          - const: mediatek,mt8192-disp-ovl-2l
28      - items:
29          - enum:
30              - mediatek,mt8186-disp-ovl-2l
31          - const: mediatek,mt8192-disp-ovl-2l
32
33  reg:
34    maxItems: 1
35
36  interrupts:
37    maxItems: 1
38
39  power-domains:
40    description: A phandle and PM domain specifier as defined by bindings of
41      the power controller specified by phandle. See
42      Documentation/devicetree/bindings/power/power-domain.yaml for details.
43
44  clocks:
45    items:
46      - description: OVL-2L Clock
47
48  iommus:
49    description:
50      This property should point to the respective IOMMU block with master port as argument,
51      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
52
53  mediatek,gce-client-reg:
54    description: The register of client driver can be configured by gce with
55      4 arguments defined in this property, such as phandle of gce, subsys id,
56      register offset and size. Each GCE subsys id is mapping to a client
57      defined in the header include/dt-bindings/gce/<chip>-gce.h.
58    $ref: /schemas/types.yaml#/definitions/phandle-array
59    maxItems: 1
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - power-domains
66  - clocks
67  - iommus
68
69additionalProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/interrupt-controller/arm-gic.h>
74    #include <dt-bindings/clock/mt8183-clk.h>
75    #include <dt-bindings/power/mt8183-power.h>
76    #include <dt-bindings/gce/mt8183-gce.h>
77    #include <dt-bindings/memory/mt8183-larb-port.h>
78
79    soc {
80        #address-cells = <2>;
81        #size-cells = <2>;
82
83        ovl_2l0: ovl@14009000 {
84            compatible = "mediatek,mt8183-disp-ovl-2l";
85            reg = <0 0x14009000 0 0x1000>;
86            interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
87            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
88            clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
89            iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
90            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
91        };
92    };
93