xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overdirve
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overdrive, namely OD, increases the transition values
15  of pixels between consecutive frames to make LCD rotate faster.
16  OD device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt2712-disp-od
26          - mediatek,mt8173-disp-od
27      - items:
28          - const: mediatek,mt6795-disp-od
29          - const: mediatek,mt8173-disp-od
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  clocks:
38    items:
39      - description: OD Clock
40
41  ports:
42    $ref: /schemas/graph.yaml#/properties/ports
43    description:
44      Input and output ports can have multiple endpoints, each of those
45      connects to either the primary, secondary, etc, display pipeline.
46
47    properties:
48      port@0:
49        $ref: /schemas/graph.yaml#/properties/port
50        description: OD input port, usually from an AAL block
51
52      port@1:
53        $ref: /schemas/graph.yaml#/properties/port
54        description:
55          OD output to the input of the next desired component in the
56          display pipeline, for example one of the available RDMA or
57          other blocks.
58
59    required:
60      - port@0
61      - port@1
62
63  mediatek,gce-client-reg:
64    $ref: /schemas/types.yaml#/definitions/phandle-array
65    description: describes how to locate the GCE client register
66    items:
67      - items:
68          - description: Phandle reference to a Mediatek GCE Mailbox
69          - description:
70              GCE subsys id mapping to a client defined in header
71              include/dt-bindings/gce/<chip>-gce.h.
72          - description: offset for the GCE register offset
73          - description: size of the GCE register offset
74
75required:
76  - compatible
77  - reg
78  - clocks
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/mt8173-clk.h>
85    #include <dt-bindings/gce/mt8173-gce.h>
86
87    soc {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        od@14023000 {
92            compatible = "mediatek,mt8173-disp-od";
93            reg = <0 0x14023000 0 0x1000>;
94            clocks = <&mmsys CLK_MM_DISP_OD>;
95            mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
96        };
97    };
98