xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display merge
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15  inputs into one side-by-side output.
16  MERGE device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-merge
26          - mediatek,mt8195-disp-merge
27          - mediatek,mt8195-mdp3-merge
28      - items:
29          - const: mediatek,mt6795-disp-merge
30          - const: mediatek,mt8173-disp-merge
31      - items:
32          - const: mediatek,mt8188-disp-merge
33          - const: mediatek,mt8195-disp-merge
34
35  reg:
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  power-domains:
42    description: A phandle and PM domain specifier as defined by bindings of
43      the power controller specified by phandle. See
44      Documentation/devicetree/bindings/power/power-domain.yaml for details.
45
46  clocks:
47    minItems: 1
48    maxItems: 2
49
50  clock-names:
51    oneOf:
52      - items:
53          - const: merge
54      - items:
55          - const: merge
56          - const: merge_async
57
58  mediatek,merge-fifo-en:
59    description:
60      The setting of merge fifo is mainly provided for the display latency
61      buffer to ensure that the back-end panel display data will not be
62      underrun, a little more data is needed in the fifo.
63      According to the merge fifo settings, when the water level is detected
64      to be insufficient, it will trigger RDMA sending ultra and preulra
65      command to SMI to speed up the data rate.
66    type: boolean
67
68  mediatek,merge-mute:
69    description: Support mute function. Mute the content of merge output.
70    type: boolean
71
72  mediatek,gce-client-reg:
73    description: The register of client driver can be configured by gce with
74      4 arguments defined in this property, such as phandle of gce, subsys id,
75      register offset and size. Each GCE subsys id is mapping to a client
76      defined in the header include/dt-bindings/gce/<chip>-gce.h.
77    $ref: /schemas/types.yaml#/definitions/phandle-array
78    maxItems: 1
79
80  ports:
81    $ref: /schemas/graph.yaml#/properties/ports
82    description:
83      Input and output ports can have multiple endpoints, each of those
84      connects to either the primary, secondary, etc, display pipeline.
85
86    properties:
87      port@0:
88        $ref: /schemas/graph.yaml#/properties/port
89        description:
90          MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
91          ETHDR or even from a different MERGE block
92
93      port@1:
94        $ref: /schemas/graph.yaml#/properties/port
95        description:
96          MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
97          a different MERGE block, or others.
98
99    required:
100      - port@0
101      - port@1
102
103  resets:
104    description: reset controller
105      See Documentation/devicetree/bindings/reset/reset.txt for details.
106    maxItems: 1
107
108required:
109  - compatible
110  - reg
111  - power-domains
112  - clocks
113
114additionalProperties: false
115
116examples:
117  - |
118    #include <dt-bindings/interrupt-controller/arm-gic.h>
119    #include <dt-bindings/clock/mt8173-clk.h>
120    #include <dt-bindings/power/mt8173-power.h>
121
122    soc {
123        #address-cells = <2>;
124        #size-cells = <2>;
125
126        merge@14017000 {
127            compatible = "mediatek,mt8173-disp-merge";
128            reg = <0 0x14017000 0 0x1000>;
129            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
130            clocks = <&mmsys CLK_MM_DISP_MERGE>;
131            clock-names = "merge";
132        };
133    };
134