1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek Ethdr Device 8 9maintainers: 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Philipp Zabel <p.zabel@pengutronix.de> 12 13description: 14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is 15 designed for HDR video and graphics conversion in the external display path. 16 It handles multiple HDR input types and performs tone mapping, color 17 space/color format conversion, and then combine different layers, 18 output the required HDR or SDR signal to the subsequent display path. 19 This engine is composed of two video frontends, two graphic frontends, 20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL. 21 These two function blocks read the pre-programmed registers from DRAM and 22 set them to HW in the v-blanking period. 23 24properties: 25 compatible: 26 const: mediatek,mt8195-disp-ethdr 27 28 reg: 29 maxItems: 7 30 31 reg-names: 32 items: 33 - const: mixer 34 - const: vdo_fe0 35 - const: vdo_fe1 36 - const: gfx_fe0 37 - const: gfx_fe1 38 - const: vdo_be 39 - const: adl_ds 40 41 interrupts: 42 maxItems: 1 43 44 iommus: 45 minItems: 1 46 maxItems: 2 47 48 clocks: 49 items: 50 - description: mixer clock 51 - description: video frontend 0 clock 52 - description: video frontend 1 clock 53 - description: graphic frontend 0 clock 54 - description: graphic frontend 1 clock 55 - description: video backend clock 56 - description: autodownload and menuload clock 57 - description: video frontend 0 async clock 58 - description: video frontend 1 async clock 59 - description: graphic frontend 0 async clock 60 - description: graphic frontend 1 async clock 61 - description: video backend async clock 62 - description: ethdr top clock 63 64 clock-names: 65 items: 66 - const: mixer 67 - const: vdo_fe0 68 - const: vdo_fe1 69 - const: gfx_fe0 70 - const: gfx_fe1 71 - const: vdo_be 72 - const: adl_ds 73 - const: vdo_fe0_async 74 - const: vdo_fe1_async 75 - const: gfx_fe0_async 76 - const: gfx_fe1_async 77 - const: vdo_be_async 78 - const: ethdr_top 79 80 power-domains: 81 maxItems: 1 82 83 resets: 84 items: 85 - description: video frontend 0 async reset 86 - description: video frontend 1 async reset 87 - description: graphic frontend 0 async reset 88 - description: graphic frontend 1 async reset 89 - description: video backend async reset 90 91 reset-names: 92 items: 93 - const: vdo_fe0_async 94 - const: vdo_fe1_async 95 - const: gfx_fe0_async 96 - const: gfx_fe1_async 97 - const: vdo_be_async 98 99 mediatek,gce-client-reg: 100 $ref: /schemas/types.yaml#/definitions/phandle-array 101 minItems: 1 102 maxItems: 7 103 description: The register of display function block to be set by gce. 104 There are 4 arguments in this property, gce node, subsys id, offset and 105 register size. The subsys id is defined in the gce header of each chips 106 include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display 107 function block. 108 109required: 110 - compatible 111 - reg 112 - clocks 113 - clock-names 114 - interrupts 115 - power-domains 116 - resets 117 - mediatek,gce-client-reg 118 119additionalProperties: false 120 121examples: 122 - | 123 #include <dt-bindings/interrupt-controller/arm-gic.h> 124 #include <dt-bindings/clock/mt8195-clk.h> 125 #include <dt-bindings/gce/mt8195-gce.h> 126 #include <dt-bindings/memory/mt8195-memory-port.h> 127 #include <dt-bindings/power/mt8195-power.h> 128 #include <dt-bindings/reset/mt8195-resets.h> 129 130 soc { 131 #address-cells = <2>; 132 #size-cells = <2>; 133 134 hdr-engine@1c114000 { 135 compatible = "mediatek,mt8195-disp-ethdr"; 136 reg = <0 0x1c114000 0 0x1000>, 137 <0 0x1c115000 0 0x1000>, 138 <0 0x1c117000 0 0x1000>, 139 <0 0x1c119000 0 0x1000>, 140 <0 0x1c11a000 0 0x1000>, 141 <0 0x1c11b000 0 0x1000>, 142 <0 0x1c11c000 0 0x1000>; 143 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 144 "vdo_be", "adl_ds"; 145 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 146 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 147 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 148 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 149 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 150 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 151 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 152 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 153 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 154 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 155 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 156 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 157 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 158 <&vdosys1 CLK_VDO1_26M_SLOW>, 159 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 160 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 161 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 162 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 163 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 164 <&topckgen CLK_TOP_ETHDR>; 165 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 166 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 167 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 168 "ethdr_top"; 169 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 170 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 171 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 172 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 173 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 174 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 175 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 176 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 177 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 178 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 179 "gfx_fe1_async", "vdo_be_async"; 180 }; 181 }; 182... 183