xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek DSI Controller Device Tree Bindings
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12  - Jitao Shi <jitao.shi@mediatek.com>
13  - Xinlei Lee <xinlei.lee@mediatek.com>
14
15description: |
16  The MediaTek DSI function block is a sink of the display subsystem and can
17  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
18  channel output.
19
20allOf:
21  - $ref: /schemas/display/dsi-controller.yaml#
22
23properties:
24  compatible:
25    enum:
26      - mediatek,mt2701-dsi
27      - mediatek,mt7623-dsi
28      - mediatek,mt8167-dsi
29      - mediatek,mt8173-dsi
30      - mediatek,mt8183-dsi
31      - mediatek,mt8186-dsi
32
33  reg:
34    maxItems: 1
35
36  interrupts:
37    maxItems: 1
38
39  power-domains:
40    maxItems: 1
41
42  clocks:
43    items:
44      - description: Engine Clock
45      - description: Digital Clock
46      - description: HS Clock
47
48  clock-names:
49    items:
50      - const: engine
51      - const: digital
52      - const: hs
53
54  resets:
55    maxItems: 1
56
57  phys:
58    maxItems: 1
59
60  phy-names:
61    items:
62      - const: dphy
63
64  port:
65    $ref: /schemas/graph.yaml#/properties/port
66    description:
67      Output port node. This port should be connected to the input
68      port of an attached DSI panel or DSI-to-eDP encoder chip.
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - power-domains
75  - clocks
76  - clock-names
77  - phys
78  - phy-names
79  - port
80
81unevaluatedProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/clock/mt8183-clk.h>
86    #include <dt-bindings/interrupt-controller/arm-gic.h>
87    #include <dt-bindings/interrupt-controller/irq.h>
88    #include <dt-bindings/power/mt8183-power.h>
89    #include <dt-bindings/phy/phy.h>
90    #include <dt-bindings/reset/mt8183-resets.h>
91
92    soc {
93        #address-cells = <2>;
94        #size-cells = <2>;
95
96        dsi0: dsi@14014000 {
97            compatible = "mediatek,mt8183-dsi";
98            reg = <0 0x14014000 0 0x1000>;
99            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
100            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
101            clocks = <&mmsys CLK_MM_DSI0_MM>,
102                <&mmsys CLK_MM_DSI0_IF>,
103                <&mipi_tx0>;
104            clock-names = "engine", "digital", "hs";
105            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
106            phys = <&mipi_tx0>;
107            phy-names = "dphy";
108            port {
109                dsi0_out: endpoint {
110                    remote-endpoint = <&panel_in>;
111                };
112            };
113        };
114    };
115
116...
117