xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml (revision bbfd5594756011167b8f8de9a00e0c946afda1e6)
19273cf7dSJitao Shi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
29273cf7dSJitao Shi%YAML 1.2
39273cf7dSJitao Shi---
49273cf7dSJitao Shi$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
59273cf7dSJitao Shi$schema: http://devicetree.org/meta-schemas/core.yaml#
69273cf7dSJitao Shi
7f294c89fSBo-Chen Chentitle: MediaTek DPI and DP_INTF Controller
89273cf7dSJitao Shi
99273cf7dSJitao Shimaintainers:
109273cf7dSJitao Shi  - CK Hu <ck.hu@mediatek.com>
119273cf7dSJitao Shi  - Jitao shi <jitao.shi@mediatek.com>
129273cf7dSJitao Shi
139273cf7dSJitao Shidescription: |
14f294c89fSBo-Chen Chen  The MediaTek DPI and DP_INTF function blocks are a sink of the display
15e32895fcSMarkus Schneider-Pargmann  subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
16e32895fcSMarkus Schneider-Pargmann  parallel output bus.
179273cf7dSJitao Shi
189273cf7dSJitao Shiproperties:
199273cf7dSJitao Shi  compatible:
20b84c6b26SAngeloGioacchino Del Regno    oneOf:
21b84c6b26SAngeloGioacchino Del Regno      - enum:
229273cf7dSJitao Shi          - mediatek,mt2701-dpi
239273cf7dSJitao Shi          - mediatek,mt7623-dpi
249273cf7dSJitao Shi          - mediatek,mt8173-dpi
259273cf7dSJitao Shi          - mediatek,mt8183-dpi
2652136021SXinlei Lee          - mediatek,mt8186-dpi
27c1a26a98Sxinlei lee          - mediatek,mt8188-dp-intf
2861865513SJitao Shi          - mediatek,mt8192-dpi
29e32895fcSMarkus Schneider-Pargmann          - mediatek,mt8195-dp-intf
3041046223SAngeloGioacchino Del Regno          - mediatek,mt8195-dpi
31b84c6b26SAngeloGioacchino Del Regno      - items:
32b84c6b26SAngeloGioacchino Del Regno          - enum:
33b84c6b26SAngeloGioacchino Del Regno              - mediatek,mt6795-dpi
34b84c6b26SAngeloGioacchino Del Regno          - const: mediatek,mt8183-dpi
35169802d2SAlexandre Mergnat      - items:
36169802d2SAlexandre Mergnat          - enum:
37169802d2SAlexandre Mergnat              - mediatek,mt8365-dpi
38169802d2SAlexandre Mergnat          - const: mediatek,mt8192-dpi
3941046223SAngeloGioacchino Del Regno      - items:
4041046223SAngeloGioacchino Del Regno          - enum:
4141046223SAngeloGioacchino Del Regno              - mediatek,mt8188-dpi
4241046223SAngeloGioacchino Del Regno          - const: mediatek,mt8195-dpi
439273cf7dSJitao Shi
449273cf7dSJitao Shi  reg:
459273cf7dSJitao Shi    maxItems: 1
469273cf7dSJitao Shi
479273cf7dSJitao Shi  interrupts:
489273cf7dSJitao Shi    maxItems: 1
499273cf7dSJitao Shi
509273cf7dSJitao Shi  clocks:
519273cf7dSJitao Shi    items:
529273cf7dSJitao Shi      - description: Pixel Clock
539273cf7dSJitao Shi      - description: Engine Clock
549273cf7dSJitao Shi      - description: DPI PLL
559273cf7dSJitao Shi
569273cf7dSJitao Shi  clock-names:
579273cf7dSJitao Shi    items:
589273cf7dSJitao Shi      - const: pixel
599273cf7dSJitao Shi      - const: engine
609273cf7dSJitao Shi      - const: pll
619273cf7dSJitao Shi
629273cf7dSJitao Shi  pinctrl-0: true
639273cf7dSJitao Shi  pinctrl-1: true
649273cf7dSJitao Shi
659273cf7dSJitao Shi  pinctrl-names:
669273cf7dSJitao Shi    items:
679273cf7dSJitao Shi      - const: default
689273cf7dSJitao Shi      - const: sleep
699273cf7dSJitao Shi
705474d49bSRohit Agarwal  power-domains:
71af6ab107SMacpaul Lin    description: |
72af6ab107SMacpaul Lin      The MediaTek DPI module is typically associated with one of the
73af6ab107SMacpaul Lin      following multimedia power domains:
74af6ab107SMacpaul Lin        POWER_DOMAIN_DISPLAY
75af6ab107SMacpaul Lin        POWER_DOMAIN_VDOSYS
76af6ab107SMacpaul Lin        POWER_DOMAIN_MM
77af6ab107SMacpaul Lin      The specific power domain used varies depending on the SoC design.
78af6ab107SMacpaul Lin
79af6ab107SMacpaul Lin      It is recommended to explicitly add the appropriate power domain
80af6ab107SMacpaul Lin      property to the DPI node in the device tree.
815474d49bSRohit Agarwal    maxItems: 1
825474d49bSRohit Agarwal
839273cf7dSJitao Shi  port:
84be7507bdSRob Herring    $ref: /schemas/graph.yaml#/properties/port
859273cf7dSJitao Shi    description:
86be7507bdSRob Herring      Output port node. This port should be connected to the input port of an
87e32895fcSMarkus Schneider-Pargmann      attached HDMI, LVDS or DisplayPort encoder chip.
889273cf7dSJitao Shi
892b6433f3SAngeloGioacchino Del Regno  ports:
902b6433f3SAngeloGioacchino Del Regno    $ref: /schemas/graph.yaml#/properties/ports
912b6433f3SAngeloGioacchino Del Regno
922b6433f3SAngeloGioacchino Del Regno    properties:
932b6433f3SAngeloGioacchino Del Regno      port@0:
942b6433f3SAngeloGioacchino Del Regno        $ref: /schemas/graph.yaml#/properties/port
952b6433f3SAngeloGioacchino Del Regno        description: DPI input port
962b6433f3SAngeloGioacchino Del Regno
972b6433f3SAngeloGioacchino Del Regno      port@1:
982b6433f3SAngeloGioacchino Del Regno        $ref: /schemas/graph.yaml#/properties/port
992b6433f3SAngeloGioacchino Del Regno        description: DPI output to an HDMI, LVDS or DisplayPort encoder input
1002b6433f3SAngeloGioacchino Del Regno
1012b6433f3SAngeloGioacchino Del Regno    required:
1022b6433f3SAngeloGioacchino Del Regno      - port@0
1032b6433f3SAngeloGioacchino Del Regno      - port@1
1042b6433f3SAngeloGioacchino Del Regno
1059273cf7dSJitao Shirequired:
1069273cf7dSJitao Shi  - compatible
1079273cf7dSJitao Shi  - reg
1089273cf7dSJitao Shi  - interrupts
1099273cf7dSJitao Shi  - clocks
1109273cf7dSJitao Shi  - clock-names
1112b6433f3SAngeloGioacchino Del Regno
1122b6433f3SAngeloGioacchino Del RegnooneOf:
1132b6433f3SAngeloGioacchino Del Regno  - required:
1149273cf7dSJitao Shi      - port
1152b6433f3SAngeloGioacchino Del Regno  - required:
1162b6433f3SAngeloGioacchino Del Regno      - ports
1179273cf7dSJitao Shi
1189273cf7dSJitao ShiadditionalProperties: false
1199273cf7dSJitao Shi
1209273cf7dSJitao Shiexamples:
1219273cf7dSJitao Shi  - |
1229273cf7dSJitao Shi    #include <dt-bindings/interrupt-controller/arm-gic.h>
1239273cf7dSJitao Shi    #include <dt-bindings/clock/mt8173-clk.h>
124*5823f045SFabien Parent    #include <dt-bindings/power/mt8173-power.h>
125bff4e302SAngeloGioacchino Del Regno
1262b6433f3SAngeloGioacchino Del Regno    dpi: dpi@1401d000 {
1279273cf7dSJitao Shi        compatible = "mediatek,mt8173-dpi";
1289273cf7dSJitao Shi        reg = <0x1401d000 0x1000>;
1299273cf7dSJitao Shi        interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
130*5823f045SFabien Parent        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1319273cf7dSJitao Shi        clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1329273cf7dSJitao Shi             <&mmsys CLK_MM_DPI_ENGINE>,
1339273cf7dSJitao Shi             <&apmixedsys CLK_APMIXED_TVDPLL>;
1349273cf7dSJitao Shi        clock-names = "pixel", "engine", "pll";
1359273cf7dSJitao Shi        pinctrl-names = "default", "sleep";
1369273cf7dSJitao Shi        pinctrl-0 = <&dpi_pin_func>;
1379273cf7dSJitao Shi        pinctrl-1 = <&dpi_pin_idle>;
1389273cf7dSJitao Shi
1399273cf7dSJitao Shi        port {
1409273cf7dSJitao Shi            dpi0_out: endpoint {
1419273cf7dSJitao Shi                remote-endpoint = <&hdmi0_in>;
1429273cf7dSJitao Shi            };
1439273cf7dSJitao Shi        };
1449273cf7dSJitao Shi    };
1459273cf7dSJitao Shi
1469273cf7dSJitao Shi...
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