xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml (revision 52a5a22d8afe3bd195f7b470c7535c63717f5ff7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Display Port Controller
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Jitao shi <jitao.shi@mediatek.com>
12
13description: |
14  MediaTek DP and eDP are different hardwares and there are some features
15  which are not supported for eDP. For example, audio is not supported for
16  eDP. Therefore, we need to use two different compatibles to describe them.
17  In addition, We just need to enable the power domain of DP, so the clock
18  of DP is generated by itself and we are not using other PLL to generate
19  clocks.
20
21properties:
22  compatible:
23    enum:
24      - mediatek,mt8188-dp-tx
25      - mediatek,mt8188-edp-tx
26      - mediatek,mt8195-dp-tx
27      - mediatek,mt8195-edp-tx
28
29  reg:
30    maxItems: 1
31
32  nvmem-cells:
33    maxItems: 1
34    description: efuse data for display port calibration
35
36  nvmem-cell-names:
37    const: dp_calibration_data
38
39  power-domains:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  '#sound-dai-cells':
46    const: 0
47
48  ports:
49    $ref: /schemas/graph.yaml#/properties/ports
50    properties:
51      port@0:
52        $ref: /schemas/graph.yaml#/properties/port
53        description: Input endpoint of the controller, usually dp_intf
54
55      port@1:
56        $ref: /schemas/graph.yaml#/$defs/port-base
57        unevaluatedProperties: false
58        description: Output endpoint of the controller
59        properties:
60          endpoint:
61            $ref: /schemas/media/video-interfaces.yaml#
62            unevaluatedProperties: false
63            properties:
64              data-lanes:
65                description: |
66                  number of lanes supported by the hardware.
67                  The possible values:
68                  0       - For 1 lane enabled in IP.
69                  0 1     - For 2 lanes enabled in IP.
70                  0 1 2 3 - For 4 lanes enabled in IP.
71                minItems: 1
72                maxItems: 4
73            required:
74              - data-lanes
75
76    required:
77      - port@0
78      - port@1
79
80  max-linkrate-mhz:
81    enum: [ 1620, 2700, 5400, 8100 ]
82    description: maximum link rate supported by the hardware.
83
84required:
85  - compatible
86  - reg
87  - interrupts
88  - ports
89  - max-linkrate-mhz
90
91allOf:
92  - $ref: /schemas/sound/dai-common.yaml#
93  - if:
94      not:
95        properties:
96          compatible:
97            contains:
98              enum:
99                - mediatek,mt8188-dp-tx
100                - mediatek,mt8195-dp-tx
101    then:
102      properties:
103        '#sound-dai-cells': false
104
105unevaluatedProperties: false
106
107examples:
108  - |
109    #include <dt-bindings/interrupt-controller/arm-gic.h>
110    #include <dt-bindings/power/mt8195-power.h>
111    dptx@1c600000 {
112        compatible = "mediatek,mt8195-dp-tx";
113        reg = <0x1c600000 0x8000>;
114        power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
115        interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
116        max-linkrate-mhz = <8100>;
117
118        ports {
119            #address-cells = <1>;
120            #size-cells = <0>;
121
122            port@0 {
123                reg = <0>;
124                dptx_in: endpoint {
125                    remote-endpoint = <&dp_intf0_out>;
126                };
127            };
128            port@1 {
129                reg = <1>;
130                dptx_out: endpoint {
131                    data-lanes = <0 1 2 3>;
132                };
133            };
134        };
135    };
136