xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display dither processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display dither processor, namely DITHER, works by approximating
15  unavailable colors with available colors and by mixing and matching available
16  colors to mimic unavailable ones.
17  DITHER device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt8183-disp-dither
27      - items:
28          - enum:
29              - mediatek,mt8167-disp-dither
30              - mediatek,mt8186-disp-dither
31              - mediatek,mt8188-disp-dither
32              - mediatek,mt8192-disp-dither
33              - mediatek,mt8195-disp-dither
34              - mediatek,mt8365-disp-dither
35          - const: mediatek,mt8183-disp-dither
36
37  reg:
38    maxItems: 1
39
40  interrupts:
41    maxItems: 1
42
43  power-domains:
44    description: A phandle and PM domain specifier as defined by bindings of
45      the power controller specified by phandle. See
46      Documentation/devicetree/bindings/power/power-domain.yaml for details.
47
48  clocks:
49    items:
50      - description: DITHER Clock
51
52  mediatek,gce-client-reg:
53    description: The register of client driver can be configured by gce with
54      4 arguments defined in this property, such as phandle of gce, subsys id,
55      register offset and size. Each GCE subsys id is mapping to a client
56      defined in the header include/dt-bindings/gce/<chip>-gce.h.
57    $ref: /schemas/types.yaml#/definitions/phandle-array
58    maxItems: 1
59
60  ports:
61    $ref: /schemas/graph.yaml#/properties/ports
62    description:
63      Input and output ports can have multiple endpoints, each of those
64      connects to either the primary, secondary, etc, display pipeline.
65
66    properties:
67      port@0:
68        $ref: /schemas/graph.yaml#/properties/port
69        description: DITHER input, usually from a POSTMASK or GAMMA block.
70
71      port@1:
72        $ref: /schemas/graph.yaml#/properties/port
73        description:
74          DITHER output to the input of the next desired component in the
75          display pipeline, for example one of the available DSC compressors,
76          DP_INTF, DSI, LVDS or others.
77
78    required:
79      - port@0
80      - port@1
81
82required:
83  - compatible
84  - reg
85  - interrupts
86  - power-domains
87  - clocks
88
89additionalProperties: false
90
91examples:
92  - |
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94    #include <dt-bindings/clock/mt8183-clk.h>
95    #include <dt-bindings/power/mt8183-power.h>
96    #include <dt-bindings/gce/mt8183-gce.h>
97
98    soc {
99        #address-cells = <2>;
100        #size-cells = <2>;
101
102        dither0: dither@14012000 {
103            compatible = "mediatek,mt8183-disp-dither";
104            reg = <0 0x14012000 0 0x1000>;
105            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
106            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
107            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
108            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
109        };
110    };
111