xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display adaptive ambient light processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display adaptive ambient light processor, namely AAL,
15  is responsible for backlight power saving and sunlight visibility improving.
16  AAL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-aal
26          - mediatek,mt8183-disp-aal
27          - mediatek,mt8195-mdp3-aal
28      - items:
29          - enum:
30              - mediatek,mt8188-mdp3-aal
31          - const: mediatek,mt8195-mdp3-aal
32      - items:
33          - enum:
34              - mediatek,mt2712-disp-aal
35              - mediatek,mt6795-disp-aal
36              - mediatek,mt8167-disp-aal
37          - const: mediatek,mt8173-disp-aal
38      - items:
39          - enum:
40              - mediatek,mt8186-disp-aal
41              - mediatek,mt8188-disp-aal
42              - mediatek,mt8192-disp-aal
43              - mediatek,mt8195-disp-aal
44              - mediatek,mt8365-disp-aal
45          - const: mediatek,mt8183-disp-aal
46
47  reg:
48    maxItems: 1
49
50  interrupts:
51    maxItems: 1
52
53  power-domains:
54    description: A phandle and PM domain specifier as defined by bindings of
55      the power controller specified by phandle. See
56      Documentation/devicetree/bindings/power/power-domain.yaml for details.
57
58  clocks:
59    items:
60      - description: AAL Clock
61
62  mediatek,gce-client-reg:
63    description: The register of client driver can be configured by gce with
64      4 arguments defined in this property, such as phandle of gce, subsys id,
65      register offset and size. Each GCE subsys id is mapping to a client
66      defined in the header include/dt-bindings/gce/<chip>-gce.h.
67    $ref: /schemas/types.yaml#/definitions/phandle-array
68    maxItems: 1
69
70  ports:
71    $ref: /schemas/graph.yaml#/properties/ports
72    description:
73      Input and output ports can have multiple endpoints, each of those
74      connects to either the primary, secondary, etc, display pipeline.
75
76    properties:
77      port@0:
78        $ref: /schemas/graph.yaml#/properties/port
79        description: AAL input port
80
81      port@1:
82        $ref: /schemas/graph.yaml#/properties/port
83        description:
84          AAL output to the next component's input, for example could be one
85          of many gamma, overdrive or other blocks.
86
87    required:
88      - port@0
89      - port@1
90
91required:
92  - compatible
93  - reg
94  - interrupts
95  - power-domains
96  - clocks
97
98additionalProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/interrupt-controller/arm-gic.h>
103    #include <dt-bindings/clock/mt8173-clk.h>
104    #include <dt-bindings/power/mt8173-power.h>
105    #include <dt-bindings/gce/mt8173-gce.h>
106
107    soc {
108        #address-cells = <2>;
109        #size-cells = <2>;
110
111        aal@14015000 {
112            compatible = "mediatek,mt8173-disp-aal";
113            reg = <0 0x14015000 0 0x1000>;
114            interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
115            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
116            clocks = <&mmsys CLK_MM_DISP_AAL>;
117            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
118
119            ports {
120                #address-cells = <1>;
121                #size-cells = <0>;
122
123                port@0 {
124                    reg = <0>;
125                    endpoint {
126                        remote-endpoint = <&ccorr0_out>;
127                    };
128                };
129
130                port@1 {
131                    reg = <1>;
132                    endpoint {
133                        remote-endpoint = <&gamma0_in>;
134                    };
135                };
136            };
137        };
138    };
139