xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml (revision d9a0788093565c300f7c8dd034dbfa6ac4da9aa6) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display adaptive ambient light processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display adaptive ambient light processor, namely AAL,
15  is responsible for backlight power saving and sunlight visibility improving.
16  AAL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-aal
26          - mediatek,mt8183-disp-aal
27          - mediatek,mt8195-mdp3-aal
28      - items:
29          - enum:
30              - mediatek,mt8188-mdp3-aal
31          - const: mediatek,mt8195-mdp3-aal
32      - items:
33          - enum:
34              - mediatek,mt2712-disp-aal
35              - mediatek,mt6795-disp-aal
36          - const: mediatek,mt8173-disp-aal
37      - items:
38          - enum:
39              - mediatek,mt8186-disp-aal
40              - mediatek,mt8188-disp-aal
41              - mediatek,mt8192-disp-aal
42              - mediatek,mt8195-disp-aal
43              - mediatek,mt8365-disp-aal
44          - const: mediatek,mt8183-disp-aal
45
46  reg:
47    maxItems: 1
48
49  interrupts:
50    maxItems: 1
51
52  power-domains:
53    description: A phandle and PM domain specifier as defined by bindings of
54      the power controller specified by phandle. See
55      Documentation/devicetree/bindings/power/power-domain.yaml for details.
56
57  clocks:
58    items:
59      - description: AAL Clock
60
61  mediatek,gce-client-reg:
62    description: The register of client driver can be configured by gce with
63      4 arguments defined in this property, such as phandle of gce, subsys id,
64      register offset and size. Each GCE subsys id is mapping to a client
65      defined in the header include/dt-bindings/gce/<chip>-gce.h.
66    $ref: /schemas/types.yaml#/definitions/phandle-array
67    maxItems: 1
68
69  ports:
70    $ref: /schemas/graph.yaml#/properties/ports
71    description:
72      Input and output ports can have multiple endpoints, each of those
73      connects to either the primary, secondary, etc, display pipeline.
74
75    properties:
76      port@0:
77        $ref: /schemas/graph.yaml#/properties/port
78        description: AAL input port
79
80      port@1:
81        $ref: /schemas/graph.yaml#/properties/port
82        description:
83          AAL output to the next component's input, for example could be one
84          of many gamma, overdrive or other blocks.
85
86    required:
87      - port@0
88      - port@1
89
90required:
91  - compatible
92  - reg
93  - interrupts
94  - power-domains
95  - clocks
96
97additionalProperties: false
98
99examples:
100  - |
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102    #include <dt-bindings/clock/mt8173-clk.h>
103    #include <dt-bindings/power/mt8173-power.h>
104    #include <dt-bindings/gce/mt8173-gce.h>
105
106    soc {
107        #address-cells = <2>;
108        #size-cells = <2>;
109
110        aal@14015000 {
111            compatible = "mediatek,mt8173-disp-aal";
112            reg = <0 0x14015000 0 0x1000>;
113            interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
114            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
115            clocks = <&mmsys CLK_MM_DISP_AAL>;
116            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
117
118            ports {
119                #address-cells = <1>;
120                #size-cells = <0>;
121
122                port@0 {
123                    reg = <0>;
124                    endpoint {
125                        remote-endpoint = <&ccorr0_out>;
126                    };
127                };
128
129                port@1 {
130                    reg = <1>;
131                    endpoint {
132                        remote-endpoint = <&gamma0_in>;
133                    };
134                };
135            };
136        };
137    };
138