xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display adaptive ambient light processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display adaptive ambient light processor, namely AAL,
15  is responsible for backlight power saving and sunlight visibility improving.
16  AAL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-aal
26          - mediatek,mt8183-disp-aal
27          - mediatek,mt8195-mdp3-aal
28      - items:
29          - enum:
30              - mediatek,mt2712-disp-aal
31              - mediatek,mt6795-disp-aal
32          - const: mediatek,mt8173-disp-aal
33      - items:
34          - enum:
35              - mediatek,mt8186-disp-aal
36              - mediatek,mt8188-disp-aal
37              - mediatek,mt8192-disp-aal
38              - mediatek,mt8195-disp-aal
39              - mediatek,mt8365-disp-aal
40          - const: mediatek,mt8183-disp-aal
41
42  reg:
43    maxItems: 1
44
45  interrupts:
46    maxItems: 1
47
48  power-domains:
49    description: A phandle and PM domain specifier as defined by bindings of
50      the power controller specified by phandle. See
51      Documentation/devicetree/bindings/power/power-domain.yaml for details.
52
53  clocks:
54    items:
55      - description: AAL Clock
56
57  mediatek,gce-client-reg:
58    description: The register of client driver can be configured by gce with
59      4 arguments defined in this property, such as phandle of gce, subsys id,
60      register offset and size. Each GCE subsys id is mapping to a client
61      defined in the header include/dt-bindings/gce/<chip>-gce.h.
62    $ref: /schemas/types.yaml#/definitions/phandle-array
63    maxItems: 1
64
65  ports:
66    $ref: /schemas/graph.yaml#/properties/ports
67    description:
68      Input and output ports can have multiple endpoints, each of those
69      connects to either the primary, secondary, etc, display pipeline.
70
71    properties:
72      port@0:
73        $ref: /schemas/graph.yaml#/properties/port
74        description: AAL input port
75
76      port@1:
77        $ref: /schemas/graph.yaml#/properties/port
78        description:
79          AAL output to the next component's input, for example could be one
80          of many gamma, overdrive or other blocks.
81
82    required:
83      - port@0
84      - port@1
85
86required:
87  - compatible
88  - reg
89  - interrupts
90  - power-domains
91  - clocks
92
93additionalProperties: false
94
95examples:
96  - |
97    #include <dt-bindings/interrupt-controller/arm-gic.h>
98    #include <dt-bindings/clock/mt8173-clk.h>
99    #include <dt-bindings/power/mt8173-power.h>
100    #include <dt-bindings/gce/mt8173-gce.h>
101
102    soc {
103        #address-cells = <2>;
104        #size-cells = <2>;
105
106        aal@14015000 {
107           compatible = "mediatek,mt8173-disp-aal";
108           reg = <0 0x14015000 0 0x1000>;
109           interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
110           power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
111           clocks = <&mmsys CLK_MM_DISP_AAL>;
112           mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
113
114           ports {
115               #address-cells = <1>;
116               #size-cells = <0>;
117
118               port@0 {
119                   reg = <0>;
120                   aal0_in: endpoint {
121                       remote-endpoint = <&ccorr0_out>;
122                   };
123               };
124
125               port@1 {
126                   reg = <1>;
127                   aal0_out: endpoint {
128                       remote-endpoint = <&gamma0_in>;
129                   };
130               };
131           };
132       };
133    };
134