xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml (revision 81d707f32eb913f3296246ab9e2e6edf1a97064b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek DSI Controller
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12  - Jitao Shi <jitao.shi@mediatek.com>
13  - Xinlei Lee <xinlei.lee@mediatek.com>
14
15description: |
16  The MediaTek DSI function block is a sink of the display subsystem and can
17  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
18  channel output.
19
20allOf:
21  - $ref: /schemas/display/dsi-controller.yaml#
22
23properties:
24  compatible:
25    oneOf:
26      - enum:
27          - mediatek,mt2701-dsi
28          - mediatek,mt7623-dsi
29          - mediatek,mt8167-dsi
30          - mediatek,mt8173-dsi
31          - mediatek,mt8183-dsi
32          - mediatek,mt8186-dsi
33          - mediatek,mt8188-dsi
34      - items:
35          - enum:
36              - mediatek,mt6795-dsi
37          - const: mediatek,mt8173-dsi
38
39  reg:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  power-domains:
46    maxItems: 1
47
48  clocks:
49    items:
50      - description: Engine Clock
51      - description: Digital Clock
52      - description: HS Clock
53
54  clock-names:
55    items:
56      - const: engine
57      - const: digital
58      - const: hs
59
60  resets:
61    maxItems: 1
62
63  phys:
64    maxItems: 1
65
66  phy-names:
67    items:
68      - const: dphy
69
70  port:
71    $ref: /schemas/graph.yaml#/properties/port
72    description:
73      Output port node. This port should be connected to the input
74      port of an attached DSI panel or DSI-to-eDP encoder chip.
75
76required:
77  - compatible
78  - reg
79  - interrupts
80  - power-domains
81  - clocks
82  - clock-names
83  - phys
84  - phy-names
85  - port
86
87unevaluatedProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/clock/mt8183-clk.h>
92    #include <dt-bindings/interrupt-controller/arm-gic.h>
93    #include <dt-bindings/interrupt-controller/irq.h>
94    #include <dt-bindings/power/mt8183-power.h>
95    #include <dt-bindings/phy/phy.h>
96    #include <dt-bindings/reset/mt8183-resets.h>
97
98    soc {
99        #address-cells = <2>;
100        #size-cells = <2>;
101
102        dsi0: dsi@14014000 {
103            compatible = "mediatek,mt8183-dsi";
104            reg = <0 0x14014000 0 0x1000>;
105            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
106            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
107            clocks = <&mmsys CLK_MM_DSI0_MM>,
108                <&mmsys CLK_MM_DSI0_IF>,
109                <&mipi_tx0>;
110            clock-names = "engine", "digital", "hs";
111            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
112            phys = <&mipi_tx0>;
113            phy-names = "dphy";
114            port {
115                dsi0_out: endpoint {
116                    remote-endpoint = <&panel_in>;
117                };
118            };
119        };
120    };
121
122...
123