xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml (revision 06d07429858317ded2db7986113a9e0129cd599b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek DSI Controller
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12  - Jitao Shi <jitao.shi@mediatek.com>
13
14description: |
15  The MediaTek DSI function block is a sink of the display subsystem and can
16  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
17  channel output.
18
19allOf:
20  - $ref: /schemas/display/dsi-controller.yaml#
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt2701-dsi
27          - mediatek,mt7623-dsi
28          - mediatek,mt8167-dsi
29          - mediatek,mt8173-dsi
30          - mediatek,mt8183-dsi
31          - mediatek,mt8186-dsi
32          - mediatek,mt8188-dsi
33      - items:
34          - enum:
35              - mediatek,mt6795-dsi
36          - const: mediatek,mt8173-dsi
37      - items:
38          - enum:
39              - mediatek,mt8195-dsi
40          - const: mediatek,mt8183-dsi
41
42  reg:
43    maxItems: 1
44
45  interrupts:
46    maxItems: 1
47
48  power-domains:
49    maxItems: 1
50
51  clocks:
52    items:
53      - description: Engine Clock
54      - description: Digital Clock
55      - description: HS Clock
56
57  clock-names:
58    items:
59      - const: engine
60      - const: digital
61      - const: hs
62
63  resets:
64    maxItems: 1
65
66  phys:
67    maxItems: 1
68
69  phy-names:
70    items:
71      - const: dphy
72
73  port:
74    $ref: /schemas/graph.yaml#/properties/port
75    description:
76      Output port node. This port should be connected to the input
77      port of an attached DSI panel or DSI-to-eDP encoder chip.
78
79required:
80  - compatible
81  - reg
82  - interrupts
83  - power-domains
84  - clocks
85  - clock-names
86  - phys
87  - phy-names
88  - port
89
90unevaluatedProperties: false
91
92examples:
93  - |
94    #include <dt-bindings/clock/mt8183-clk.h>
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96    #include <dt-bindings/interrupt-controller/irq.h>
97    #include <dt-bindings/power/mt8183-power.h>
98    #include <dt-bindings/phy/phy.h>
99    #include <dt-bindings/reset/mt8183-resets.h>
100
101    soc {
102        #address-cells = <2>;
103        #size-cells = <2>;
104
105        dsi0: dsi@14014000 {
106            compatible = "mediatek,mt8183-dsi";
107            reg = <0 0x14014000 0 0x1000>;
108            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
109            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
110            clocks = <&mmsys CLK_MM_DSI0_MM>,
111                <&mmsys CLK_MM_DSI0_IF>,
112                <&mipi_tx0>;
113            clock-names = "engine", "digital", "hs";
114            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
115            phys = <&mipi_tx0>;
116            phy-names = "dphy";
117            port {
118                dsi0_out: endpoint {
119                    remote-endpoint = <&panel_in>;
120                };
121            };
122        };
123    };
124
125...
126