xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml (revision ff32fcca64437f679a2bf1c0a19d5def389a18e2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display dither processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display dither processor, namely DITHER, works by approximating
15  unavailable colors with available colors and by mixing and matching available
16  colors to mimic unavailable ones.
17  DITHER device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt8183-disp-dither
27      - items:
28          - enum:
29              - mediatek,mt8186-disp-dither
30              - mediatek,mt8188-disp-dither
31              - mediatek,mt8192-disp-dither
32              - mediatek,mt8195-disp-dither
33          - const: mediatek,mt8183-disp-dither
34
35  reg:
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  power-domains:
42    description: A phandle and PM domain specifier as defined by bindings of
43      the power controller specified by phandle. See
44      Documentation/devicetree/bindings/power/power-domain.yaml for details.
45
46  clocks:
47    items:
48      - description: DITHER Clock
49
50  mediatek,gce-client-reg:
51    description: The register of client driver can be configured by gce with
52      4 arguments defined in this property, such as phandle of gce, subsys id,
53      register offset and size. Each GCE subsys id is mapping to a client
54      defined in the header include/dt-bindings/gce/<chip>-gce.h.
55    $ref: /schemas/types.yaml#/definitions/phandle-array
56    maxItems: 1
57
58required:
59  - compatible
60  - reg
61  - interrupts
62  - power-domains
63  - clocks
64
65additionalProperties: false
66
67examples:
68  - |
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70    #include <dt-bindings/clock/mt8183-clk.h>
71    #include <dt-bindings/power/mt8183-power.h>
72    #include <dt-bindings/gce/mt8183-gce.h>
73
74    soc {
75        #address-cells = <2>;
76        #size-cells = <2>;
77
78        dither0: dither@14012000 {
79            compatible = "mediatek,mt8183-disp-dither";
80            reg = <0 0x14012000 0 0x1000>;
81            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
82            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
83            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
84            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
85        };
86    };
87