1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: LVDS Data Mapping 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 - Thierry Reding <thierry.reding@gmail.com> 12 13description: | 14 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 15 incompatible data link layers have been used over time to transmit image data 16 to LVDS devices. This bindings supports devices compatible with the following 17 specifications. 18 19 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 20 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 21 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 22 Semiconductor 23 [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 24 Electronics Standards Association (VESA) 25 26 Device compatible with those specifications have been marketed under the 27 FPD-Link and FlatLink brands. 28 29 This bindings also supports 30-bit data mapping compatible with JEIDA and 30 VESA. 31 32properties: 33 data-mapping: 34 enum: 35 - jeida-18 36 - jeida-24 37 - jeida-30 38 - vesa-24 39 - vesa-30 40 description: | 41 The color signals mapping order. 42 43 LVDS data mappings are defined as follows. 44 45 - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 46 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 47 48 Slot 0 1 2 3 4 5 6 49 ________________ _________________ 50 Clock \_______________________/ 51 ______ ______ ______ ______ ______ ______ ______ 52 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 53 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 54 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 55 56 - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 57 specifications. Data are transferred as follows on 4 LVDS lanes. 58 59 Slot 0 1 2 3 4 5 6 60 ________________ _________________ 61 Clock \_______________________/ 62 ______ ______ ______ ______ ______ ______ ______ 63 DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 64 DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 65 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 66 DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 67 68 - "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data 69 are transferred as follows on 5 LVDS lanes. 70 71 Slot 0 1 2 3 4 5 6 72 ________________ _________________ 73 Clock \_______________________/ 74 ______ ______ ______ ______ ______ ______ ______ 75 DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__>< 76 DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__>< 77 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__>< 78 DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__>< 79 DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 80 81 - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 82 Data are transferred as follows on 4 LVDS lanes. 83 84 Slot 0 1 2 3 4 5 6 85 ________________ _________________ 86 Clock \_______________________/ 87 ______ ______ ______ ______ ______ ______ ______ 88 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 89 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 90 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 91 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 92 93 - "vesa-30" - 30-bit data mapping compatible with VESA. Data are 94 transferred as follows on 5 LVDS lanes. 95 96 Slot 0 1 2 3 4 5 6 97 ________________ _________________ 98 Clock \_______________________/ 99 ______ ______ ______ ______ ______ ______ ______ 100 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 101 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 102 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 103 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 104 DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__>< 105 106 Control signals are mapped as follows. 107 108 CTL0: HSync 109 CTL1: VSync 110 CTL2: Data Enable 111 CTL3: 0 112 113additionalProperties: true 114 115... 116