1*1c0ff333SLiu Ying# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1c0ff333SLiu Ying%YAML 1.2 3*1c0ff333SLiu Ying--- 4*1c0ff333SLiu Ying$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml# 5*1c0ff333SLiu Ying$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1c0ff333SLiu Ying 7*1c0ff333SLiu Yingtitle: Freescale i.MX8qxp Display Controller External Destination Interface 8*1c0ff333SLiu Ying 9*1c0ff333SLiu Yingdescription: | 10*1c0ff333SLiu Ying The External Destination unit is the interface between the internal pixel 11*1c0ff333SLiu Ying processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha, 12*1c0ff333SLiu Ying and a Display Engine. 13*1c0ff333SLiu Ying 14*1c0ff333SLiu Ying It comprises the following built-in Gamma apply function. 15*1c0ff333SLiu Ying 16*1c0ff333SLiu Ying +------X-----------------------+ 17*1c0ff333SLiu Ying | | ExtDst Unit | 18*1c0ff333SLiu Ying | V | 19*1c0ff333SLiu Ying | +-------+ | 20*1c0ff333SLiu Ying | | Gamma | | 21*1c0ff333SLiu Ying | +-------+ | 22*1c0ff333SLiu Ying | | | 23*1c0ff333SLiu Ying | V + 24*1c0ff333SLiu Ying +------X-----------------------+ 25*1c0ff333SLiu Ying 26*1c0ff333SLiu Ying The output format is 24-bit RGB plus 1-bit Alpha. Conversion from 10 to 8 27*1c0ff333SLiu Ying bits is done by LSBit truncation. Alpha output bit is 1 for input 255, 0 28*1c0ff333SLiu Ying otherwise. 29*1c0ff333SLiu Ying 30*1c0ff333SLiu Yingmaintainers: 31*1c0ff333SLiu Ying - Liu Ying <victor.liu@nxp.com> 32*1c0ff333SLiu Ying 33*1c0ff333SLiu Yingproperties: 34*1c0ff333SLiu Ying compatible: 35*1c0ff333SLiu Ying const: fsl,imx8qxp-dc-extdst 36*1c0ff333SLiu Ying 37*1c0ff333SLiu Ying reg: 38*1c0ff333SLiu Ying maxItems: 2 39*1c0ff333SLiu Ying 40*1c0ff333SLiu Ying reg-names: 41*1c0ff333SLiu Ying items: 42*1c0ff333SLiu Ying - const: pec 43*1c0ff333SLiu Ying - const: cfg 44*1c0ff333SLiu Ying 45*1c0ff333SLiu Ying interrupts: 46*1c0ff333SLiu Ying maxItems: 3 47*1c0ff333SLiu Ying 48*1c0ff333SLiu Ying interrupt-names: 49*1c0ff333SLiu Ying items: 50*1c0ff333SLiu Ying - const: shdload 51*1c0ff333SLiu Ying - const: framecomplete 52*1c0ff333SLiu Ying - const: seqcomplete 53*1c0ff333SLiu Ying 54*1c0ff333SLiu Yingrequired: 55*1c0ff333SLiu Ying - compatible 56*1c0ff333SLiu Ying - reg 57*1c0ff333SLiu Ying - reg-names 58*1c0ff333SLiu Ying - interrupts 59*1c0ff333SLiu Ying - interrupt-names 60*1c0ff333SLiu Ying 61*1c0ff333SLiu YingadditionalProperties: false 62*1c0ff333SLiu Ying 63*1c0ff333SLiu Yingexamples: 64*1c0ff333SLiu Ying - | 65*1c0ff333SLiu Ying extdst@56180980 { 66*1c0ff333SLiu Ying compatible = "fsl,imx8qxp-dc-extdst"; 67*1c0ff333SLiu Ying reg = <0x56180980 0x1c>, <0x56184800 0x28>; 68*1c0ff333SLiu Ying reg-names = "pec", "cfg"; 69*1c0ff333SLiu Ying interrupt-parent = <&dc0_intc>; 70*1c0ff333SLiu Ying interrupts = <3>, <4>, <5>; 71*1c0ff333SLiu Ying interrupt-names = "shdload", "framecomplete", "seqcomplete"; 72*1c0ff333SLiu Ying }; 73