xref: /linux/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml (revision 75b1a8f9d62e50f05d0e4e9f3c8bcde32527ffc1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Thine Electronics THC63LVD1024 LVDS Decoder
8
9maintainers:
10  - Jacopo Mondi <jacopo+renesas@jmondi.org>
11  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12
13description: |
14  The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15  streams to parallel data outputs. The chip supports single/dual input/output
16  modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
17  outputs.
18
19  Single or dual operation mode, output data mapping and DDR output modes are
20  configured through input signals and the chip does not expose any control
21  bus.
22
23properties:
24  compatible:
25    const: thine,thc63lvd1024
26
27  ports:
28    type: object
29    description: |
30      This device has four video ports. Their connections are modeled using the
31      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
32
33      The device can operate in single-link mode or dual-link mode. In
34      single-link mode, all pixels are received on port@0, and port@1 shall not
35      contain any endpoint. In dual-link mode, even-numbered pixels are
36      received on port@0 and odd-numbered pixels on port@1, and both port@0 and
37      port@1 shall contain endpoints.
38
39    properties:
40      '#address-cells':
41        const: 1
42
43      '#size-cells':
44        const: 0
45
46      port@0:
47        type: object
48        description: First LVDS input port
49
50      port@1:
51        type: object
52        description: Second LVDS input port
53
54      port@2:
55        type: object
56        description: First digital CMOS/TTL parallel output
57
58      port@3:
59        type: object
60        description: Second digital CMOS/TTL parallel output
61
62    required:
63      - port@0
64      - port@2
65
66    additionalProperties: false
67
68  oe-gpios:
69    maxItems: 1
70    description: Output enable GPIO signal, pin name "OE", active high.
71
72  powerdown-gpios:
73    maxItems: 1
74    description: Power down GPIO signal, pin name "/PDWN", active low.
75
76  vcc-supply:
77    description:
78      Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
79      digital circuitry.
80
81required:
82  - compatible
83  - ports
84  - vcc-supply
85
86additionalProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/gpio/gpio.h>
91
92    lvds-decoder {
93        compatible = "thine,thc63lvd1024";
94
95        vcc-supply = <&reg_lvds_vcc>;
96        powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
97
98        ports {
99            #address-cells = <1>;
100            #size-cells = <0>;
101
102            port@0 {
103                reg = <0>;
104
105                lvds_dec_in_0: endpoint {
106                    remote-endpoint = <&lvds_out>;
107                };
108            };
109
110            port@2 {
111                reg = <2>;
112
113                lvds_dec_out_2: endpoint {
114                    remote-endpoint = <&adv7511_in>;
115                };
116            };
117        };
118    };
119
120...
121