xref: /linux/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml (revision 10205618052908770451acd33eaeaa7685e97ed2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Thine Electronics THC63LVD1024 LVDS Decoder
8
9maintainers:
10  - Jacopo Mondi <jacopo+renesas@jmondi.org>
11  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12
13description: |
14  The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15  streams to parallel data outputs. The chip supports single/dual input/output
16  modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
17  outputs.
18
19  Single or dual operation mode, output data mapping and DDR output modes are
20  configured through input signals and the chip does not expose any control
21  bus.
22
23properties:
24  compatible:
25    const: thine,thc63lvd1024
26
27  ports:
28    type: object
29    description: |
30      This device has four video ports. Their connections are modeled using the
31      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
32
33      The device can operate in single or dual input and output modes.
34
35      When operating in single input mode, all pixels are received on port@0,
36      and port@1 shall not contain any endpoint. In dual input mode,
37      even-numbered pixels are received on port@0 and odd-numbered pixels on
38      port@1, and both port@0 and port@1 shall contain endpoints.
39
40      When operating in single output mode all pixels are output from the first
41      CMOS/TTL port and port@3 shall not contain any endpoint. In dual output
42      mode pixels are output from both CMOS/TTL ports and both port@2 and
43      port@3 shall contain endpoints.
44
45    properties:
46      '#address-cells':
47        const: 1
48
49      '#size-cells':
50        const: 0
51
52      port@0:
53        type: object
54        description: First LVDS input port
55
56      port@1:
57        type: object
58        description: Second LVDS input port
59
60      port@2:
61        type: object
62        description: First digital CMOS/TTL parallel output
63
64      port@3:
65        type: object
66        description: Second digital CMOS/TTL parallel output
67
68    required:
69      - port@0
70      - port@2
71
72    additionalProperties: false
73
74  oe-gpios:
75    maxItems: 1
76    description: Output enable GPIO signal, pin name "OE", active high.
77
78  powerdown-gpios:
79    maxItems: 1
80    description: Power down GPIO signal, pin name "/PDWN", active low.
81
82  vcc-supply:
83    description:
84      Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
85      digital circuitry.
86
87required:
88  - compatible
89  - ports
90  - vcc-supply
91
92additionalProperties: false
93
94examples:
95  - |
96    #include <dt-bindings/gpio/gpio.h>
97
98    lvds-decoder {
99        compatible = "thine,thc63lvd1024";
100
101        vcc-supply = <&reg_lvds_vcc>;
102        powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
103
104        ports {
105            #address-cells = <1>;
106            #size-cells = <0>;
107
108            port@0 {
109                reg = <0>;
110
111                lvds_dec_in_0: endpoint {
112                    remote-endpoint = <&lvds_out>;
113                };
114            };
115
116            port@2 {
117                reg = <2>;
118
119                lvds_dec_out_2: endpoint {
120                    remote-endpoint = <&adv7511_in>;
121                };
122            };
123        };
124    };
125
126...
127