1*7f9321ffSLaurent Pinchart# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*7f9321ffSLaurent Pinchart%YAML 1.2 3*7f9321ffSLaurent Pinchart--- 4*7f9321ffSLaurent Pinchart$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# 5*7f9321ffSLaurent Pinchart$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7f9321ffSLaurent Pinchart 7*7f9321ffSLaurent Pincharttitle: Common Properties for Synopsys DesignWare HDMI TX Controller 8*7f9321ffSLaurent Pinchart 9*7f9321ffSLaurent Pinchartmaintainers: 10*7f9321ffSLaurent Pinchart - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*7f9321ffSLaurent Pinchart 12*7f9321ffSLaurent Pinchartdescription: | 13*7f9321ffSLaurent Pinchart This document defines device tree properties for the Synopsys DesignWare HDMI 14*7f9321ffSLaurent Pinchart TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree 15*7f9321ffSLaurent Pinchart binding specification by itself but is meant to be referenced by device tree 16*7f9321ffSLaurent Pinchart bindings for the platform-specific integrations of the DWC HDMI TX. 17*7f9321ffSLaurent Pinchart 18*7f9321ffSLaurent Pinchart When referenced from platform device tree bindings the properties defined in 19*7f9321ffSLaurent Pinchart this document are defined as follows. The platform device tree bindings are 20*7f9321ffSLaurent Pinchart responsible for defining whether each property is required or optional. 21*7f9321ffSLaurent Pinchart 22*7f9321ffSLaurent Pinchartproperties: 23*7f9321ffSLaurent Pinchart reg: 24*7f9321ffSLaurent Pinchart maxItems: 1 25*7f9321ffSLaurent Pinchart 26*7f9321ffSLaurent Pinchart reg-io-width: 27*7f9321ffSLaurent Pinchart description: 28*7f9321ffSLaurent Pinchart Width (in bytes) of the registers specified by the reg property. 29*7f9321ffSLaurent Pinchart allOf: 30*7f9321ffSLaurent Pinchart - $ref: /schemas/types.yaml#/definitions/uint32 31*7f9321ffSLaurent Pinchart - enum: [1, 4] 32*7f9321ffSLaurent Pinchart default: 1 33*7f9321ffSLaurent Pinchart 34*7f9321ffSLaurent Pinchart clocks: 35*7f9321ffSLaurent Pinchart minItems: 2 36*7f9321ffSLaurent Pinchart maxItems: 5 37*7f9321ffSLaurent Pinchart items: 38*7f9321ffSLaurent Pinchart - description: The bus clock for either AHB and APB 39*7f9321ffSLaurent Pinchart - description: The internal register configuration clock 40*7f9321ffSLaurent Pinchart additionalItems: true 41*7f9321ffSLaurent Pinchart 42*7f9321ffSLaurent Pinchart clock-names: 43*7f9321ffSLaurent Pinchart minItems: 2 44*7f9321ffSLaurent Pinchart maxItems: 5 45*7f9321ffSLaurent Pinchart items: 46*7f9321ffSLaurent Pinchart - const: iahb 47*7f9321ffSLaurent Pinchart - const: isfr 48*7f9321ffSLaurent Pinchart additionalItems: true 49*7f9321ffSLaurent Pinchart 50*7f9321ffSLaurent Pinchart interrupts: 51*7f9321ffSLaurent Pinchart maxItems: 1 52*7f9321ffSLaurent Pinchart 53*7f9321ffSLaurent PinchartadditionalProperties: true 54*7f9321ffSLaurent Pinchart 55*7f9321ffSLaurent Pinchart... 56