17f9321ffSLaurent Pinchart# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 27f9321ffSLaurent Pinchart%YAML 1.2 37f9321ffSLaurent Pinchart--- 47f9321ffSLaurent Pinchart$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# 57f9321ffSLaurent Pinchart$schema: http://devicetree.org/meta-schemas/core.yaml# 67f9321ffSLaurent Pinchart 77f9321ffSLaurent Pincharttitle: Common Properties for Synopsys DesignWare HDMI TX Controller 87f9321ffSLaurent Pinchart 97f9321ffSLaurent Pinchartmaintainers: 107f9321ffSLaurent Pinchart - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 117f9321ffSLaurent Pinchart 127f9321ffSLaurent Pinchartdescription: | 137f9321ffSLaurent Pinchart This document defines device tree properties for the Synopsys DesignWare HDMI 147f9321ffSLaurent Pinchart TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree 157f9321ffSLaurent Pinchart binding specification by itself but is meant to be referenced by device tree 167f9321ffSLaurent Pinchart bindings for the platform-specific integrations of the DWC HDMI TX. 177f9321ffSLaurent Pinchart 187f9321ffSLaurent Pinchart When referenced from platform device tree bindings the properties defined in 197f9321ffSLaurent Pinchart this document are defined as follows. The platform device tree bindings are 207f9321ffSLaurent Pinchart responsible for defining whether each property is required or optional. 217f9321ffSLaurent Pinchart 227f9321ffSLaurent Pinchartproperties: 237f9321ffSLaurent Pinchart reg: 247f9321ffSLaurent Pinchart maxItems: 1 257f9321ffSLaurent Pinchart 267f9321ffSLaurent Pinchart reg-io-width: 277f9321ffSLaurent Pinchart description: 287f9321ffSLaurent Pinchart Width (in bytes) of the registers specified by the reg property. 29dca66935SRob Herring enum: [1, 4] 307f9321ffSLaurent Pinchart default: 1 317f9321ffSLaurent Pinchart 327f9321ffSLaurent Pinchart clocks: 337f9321ffSLaurent Pinchart minItems: 2 347f9321ffSLaurent Pinchart maxItems: 5 357f9321ffSLaurent Pinchart items: 367f9321ffSLaurent Pinchart - description: The bus clock for either AHB and APB 377f9321ffSLaurent Pinchart - description: The internal register configuration clock 387f9321ffSLaurent Pinchart additionalItems: true 397f9321ffSLaurent Pinchart 407f9321ffSLaurent Pinchart clock-names: 417f9321ffSLaurent Pinchart minItems: 2 427f9321ffSLaurent Pinchart maxItems: 5 437f9321ffSLaurent Pinchart items: 447f9321ffSLaurent Pinchart - const: iahb 457f9321ffSLaurent Pinchart - const: isfr 467f9321ffSLaurent Pinchart additionalItems: true 477f9321ffSLaurent Pinchart 48*4c3f53edSMarek Vasut ddc-i2c-bus: 49*4c3f53edSMarek Vasut $ref: /schemas/types.yaml#/definitions/phandle 50*4c3f53edSMarek Vasut description: 51*4c3f53edSMarek Vasut The HDMI DDC bus can be connected to either a system I2C master or the 52*4c3f53edSMarek Vasut functionally-reduced I2C master contained in the DWC HDMI. When connected 53*4c3f53edSMarek Vasut to a system I2C master this property contains a phandle to that I2C 54*4c3f53edSMarek Vasut master controller. 55*4c3f53edSMarek Vasut 567f9321ffSLaurent Pinchart interrupts: 577f9321ffSLaurent Pinchart maxItems: 1 587f9321ffSLaurent Pinchart 597f9321ffSLaurent PinchartadditionalProperties: true 607f9321ffSLaurent Pinchart 617f9321ffSLaurent Pinchart... 62