1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car MIPI DSI/CSI-2 Encoder 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 12description: | 13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas 14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up 15 to four data lanes. 16 17allOf: 18 - $ref: /schemas/display/dsi-controller.yaml# 19 20properties: 21 compatible: 22 enum: 23 - renesas,r8a779a0-dsi-csi2-tx # for V3U 24 - renesas,r8a779g0-dsi-csi2-tx # for V4H 25 - renesas,r8a779h0-dsi-csi2-tx # for V4M 26 27 reg: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: Functional clock 33 - description: DSI (and CSI-2) functional clock 34 - description: PLL reference clock 35 36 clock-names: 37 items: 38 - const: fck 39 - const: dsi 40 - const: pll 41 42 power-domains: 43 maxItems: 1 44 45 resets: 46 maxItems: 1 47 48 ports: 49 $ref: /schemas/graph.yaml#/properties/ports 50 51 properties: 52 port@0: 53 $ref: /schemas/graph.yaml#/properties/port 54 description: Parallel input port 55 56 port@1: 57 $ref: /schemas/graph.yaml#/$defs/port-base 58 unevaluatedProperties: false 59 description: DSI/CSI-2 output port 60 61 properties: 62 endpoint: 63 $ref: /schemas/media/video-interfaces.yaml# 64 unevaluatedProperties: false 65 66 properties: 67 data-lanes: 68 minItems: 1 69 maxItems: 4 70 71 required: 72 - data-lanes 73 74 required: 75 - port@0 76 - port@1 77 78required: 79 - compatible 80 - reg 81 - clocks 82 - power-domains 83 - resets 84 - ports 85 86unevaluatedProperties: false 87 88examples: 89 - | 90 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 91 #include <dt-bindings/power/r8a779a0-sysc.h> 92 93 dsi@fed80000 { 94 compatible = "renesas,r8a779a0-dsi-csi2-tx"; 95 reg = <0xfed80000 0x10000>; 96 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 97 clocks = <&cpg CPG_MOD 415>, 98 <&cpg CPG_CORE R8A779A0_CLK_DSI>, 99 <&cpg CPG_CORE R8A779A0_CLK_CP>; 100 clock-names = "fck", "dsi", "pll"; 101 resets = <&cpg 415>; 102 103 ports { 104 #address-cells = <1>; 105 #size-cells = <0>; 106 107 port@0 { 108 reg = <0>; 109 dsi0_in: endpoint { 110 remote-endpoint = <&du_out_dsi0>; 111 }; 112 }; 113 114 port@1 { 115 reg = <1>; 116 dsi0_out: endpoint { 117 data-lanes = <1 2>; 118 remote-endpoint = <&sn65dsi86_in>; 119 }; 120 }; 121 }; 122 }; 123 124 - | 125 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 126 #include <dt-bindings/power/r8a779g0-sysc.h> 127 128 dsi@fed80000 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 compatible = "renesas,r8a779g0-dsi-csi2-tx"; 132 reg = <0xfed80000 0x10000>; 133 clocks = <&cpg CPG_MOD 415>, 134 <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, 135 <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; 136 clock-names = "fck", "dsi", "pll"; 137 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 138 resets = <&cpg 415>; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 port@0 { 145 reg = <0>; 146 }; 147 148 port@1 { 149 reg = <1>; 150 151 dsi0port1_out: endpoint { 152 remote-endpoint = <&panel_in>; 153 data-lanes = <1 2>; 154 }; 155 }; 156 }; 157 158 panel@0 { 159 reg = <0>; 160 compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c"; 161 power-supply = <&vcc_lcd_reg>; 162 163 port { 164 panel_in: endpoint { 165 remote-endpoint = <&dsi0port1_out>; 166 }; 167 }; 168 }; 169 }; 170... 171