1*0a86a4d1SLiu Ying# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*0a86a4d1SLiu Ying%YAML 1.2 3*0a86a4d1SLiu Ying--- 4*0a86a4d1SLiu Ying$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml# 5*0a86a4d1SLiu Ying$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0a86a4d1SLiu Ying 7*0a86a4d1SLiu Yingtitle: ITE IT6263 LVDS to HDMI converter 8*0a86a4d1SLiu Ying 9*0a86a4d1SLiu Yingmaintainers: 10*0a86a4d1SLiu Ying - Liu Ying <victor.liu@nxp.com> 11*0a86a4d1SLiu Ying 12*0a86a4d1SLiu Yingdescription: | 13*0a86a4d1SLiu Ying The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS 14*0a86a4d1SLiu Ying to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter, 15*0a86a4d1SLiu Ying the IT6263 supports LVDS input and HDMI 1.4 output by conversion function. 16*0a86a4d1SLiu Ying The built-in LVDS receiver can support single-link and dual-link LVDS inputs, 17*0a86a4d1SLiu Ying and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP 18*0a86a4d1SLiu Ying 1.2 and backward compatible with DVI 1.0 specification. 19*0a86a4d1SLiu Ying 20*0a86a4d1SLiu Ying The IT6263 also encodes and transmits up to 8 channels of I2S digital audio, 21*0a86a4d1SLiu Ying with sampling rate up to 192KHz and sample size up to 24 bits. In addition, 22*0a86a4d1SLiu Ying an S/PDIF input port takes in compressed audio of up to 192KHz frame rate. 23*0a86a4d1SLiu Ying 24*0a86a4d1SLiu Ying The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is 25*0a86a4d1SLiu Ying provided by the IT6263 in two interfaces: the four I2S input ports or the 26*0a86a4d1SLiu Ying S/PDIF input port. With both interfaces the highest possible HBR frame rate 27*0a86a4d1SLiu Ying is supported at up to 768KHz. 28*0a86a4d1SLiu Ying 29*0a86a4d1SLiu YingallOf: 30*0a86a4d1SLiu Ying - $ref: /schemas/display/lvds-dual-ports.yaml# 31*0a86a4d1SLiu Ying 32*0a86a4d1SLiu Yingproperties: 33*0a86a4d1SLiu Ying compatible: 34*0a86a4d1SLiu Ying const: ite,it6263 35*0a86a4d1SLiu Ying 36*0a86a4d1SLiu Ying reg: 37*0a86a4d1SLiu Ying maxItems: 1 38*0a86a4d1SLiu Ying 39*0a86a4d1SLiu Ying clocks: 40*0a86a4d1SLiu Ying maxItems: 1 41*0a86a4d1SLiu Ying description: audio master clock 42*0a86a4d1SLiu Ying 43*0a86a4d1SLiu Ying clock-names: 44*0a86a4d1SLiu Ying const: mclk 45*0a86a4d1SLiu Ying 46*0a86a4d1SLiu Ying data-mapping: 47*0a86a4d1SLiu Ying enum: 48*0a86a4d1SLiu Ying - jeida-18 49*0a86a4d1SLiu Ying - jeida-24 50*0a86a4d1SLiu Ying - jeida-30 51*0a86a4d1SLiu Ying - vesa-24 52*0a86a4d1SLiu Ying - vesa-30 53*0a86a4d1SLiu Ying 54*0a86a4d1SLiu Ying reset-gpios: 55*0a86a4d1SLiu Ying maxItems: 1 56*0a86a4d1SLiu Ying 57*0a86a4d1SLiu Ying ivdd-supply: 58*0a86a4d1SLiu Ying description: 1.8V digital logic power 59*0a86a4d1SLiu Ying 60*0a86a4d1SLiu Ying ovdd-supply: 61*0a86a4d1SLiu Ying description: 3.3V I/O pin power 62*0a86a4d1SLiu Ying 63*0a86a4d1SLiu Ying txavcc18-supply: 64*0a86a4d1SLiu Ying description: 1.8V HDMI analog frontend power 65*0a86a4d1SLiu Ying 66*0a86a4d1SLiu Ying txavcc33-supply: 67*0a86a4d1SLiu Ying description: 3.3V HDMI analog frontend power 68*0a86a4d1SLiu Ying 69*0a86a4d1SLiu Ying pvcc1-supply: 70*0a86a4d1SLiu Ying description: 1.8V HDMI frontend core PLL power 71*0a86a4d1SLiu Ying 72*0a86a4d1SLiu Ying pvcc2-supply: 73*0a86a4d1SLiu Ying description: 1.8V HDMI frontend filter PLL power 74*0a86a4d1SLiu Ying 75*0a86a4d1SLiu Ying avcc-supply: 76*0a86a4d1SLiu Ying description: 3.3V LVDS frontend power 77*0a86a4d1SLiu Ying 78*0a86a4d1SLiu Ying anvdd-supply: 79*0a86a4d1SLiu Ying description: 1.8V LVDS frontend analog power 80*0a86a4d1SLiu Ying 81*0a86a4d1SLiu Ying apvdd-supply: 82*0a86a4d1SLiu Ying description: 1.8V LVDS frontend PLL power 83*0a86a4d1SLiu Ying 84*0a86a4d1SLiu Ying "#sound-dai-cells": 85*0a86a4d1SLiu Ying const: 0 86*0a86a4d1SLiu Ying 87*0a86a4d1SLiu Ying ite,i2s-audio-fifo-sources: 88*0a86a4d1SLiu Ying $ref: /schemas/types.yaml#/definitions/uint32-array 89*0a86a4d1SLiu Ying minItems: 1 90*0a86a4d1SLiu Ying maxItems: 4 91*0a86a4d1SLiu Ying items: 92*0a86a4d1SLiu Ying enum: [0, 1, 2, 3] 93*0a86a4d1SLiu Ying description: 94*0a86a4d1SLiu Ying Each array element indicates the pin number of an I2S serial data input 95*0a86a4d1SLiu Ying line which is connected to an audio FIFO, from audio FIFO0 to FIFO3. 96*0a86a4d1SLiu Ying 97*0a86a4d1SLiu Ying ite,rl-channel-swap-audio-sources: 98*0a86a4d1SLiu Ying $ref: /schemas/types.yaml#/definitions/uint32-array 99*0a86a4d1SLiu Ying minItems: 1 100*0a86a4d1SLiu Ying maxItems: 4 101*0a86a4d1SLiu Ying uniqueItems: true 102*0a86a4d1SLiu Ying items: 103*0a86a4d1SLiu Ying enum: [0, 1, 2, 3] 104*0a86a4d1SLiu Ying description: 105*0a86a4d1SLiu Ying Each array element indicates an audio source whose right channel and left 106*0a86a4d1SLiu Ying channel are swapped by this converter. For I2S, the element is the pin 107*0a86a4d1SLiu Ying number of an I2S serial data input line. For S/PDIF, the element is always 108*0a86a4d1SLiu Ying 0. 109*0a86a4d1SLiu Ying 110*0a86a4d1SLiu Ying ports: 111*0a86a4d1SLiu Ying $ref: /schemas/graph.yaml#/properties/ports 112*0a86a4d1SLiu Ying 113*0a86a4d1SLiu Ying properties: 114*0a86a4d1SLiu Ying port@0: true 115*0a86a4d1SLiu Ying 116*0a86a4d1SLiu Ying port@1: 117*0a86a4d1SLiu Ying oneOf: 118*0a86a4d1SLiu Ying - required: [dual-lvds-odd-pixels] 119*0a86a4d1SLiu Ying - required: [dual-lvds-even-pixels] 120*0a86a4d1SLiu Ying 121*0a86a4d1SLiu Ying port@2: 122*0a86a4d1SLiu Ying $ref: /schemas/graph.yaml#/properties/port 123*0a86a4d1SLiu Ying description: video port for the HDMI output 124*0a86a4d1SLiu Ying 125*0a86a4d1SLiu Ying port@3: 126*0a86a4d1SLiu Ying $ref: /schemas/graph.yaml#/properties/port 127*0a86a4d1SLiu Ying description: sound input port 128*0a86a4d1SLiu Ying 129*0a86a4d1SLiu Ying required: 130*0a86a4d1SLiu Ying - port@0 131*0a86a4d1SLiu Ying - port@2 132*0a86a4d1SLiu Ying 133*0a86a4d1SLiu Yingrequired: 134*0a86a4d1SLiu Ying - compatible 135*0a86a4d1SLiu Ying - reg 136*0a86a4d1SLiu Ying - data-mapping 137*0a86a4d1SLiu Ying - ivdd-supply 138*0a86a4d1SLiu Ying - ovdd-supply 139*0a86a4d1SLiu Ying - txavcc18-supply 140*0a86a4d1SLiu Ying - txavcc33-supply 141*0a86a4d1SLiu Ying - pvcc1-supply 142*0a86a4d1SLiu Ying - pvcc2-supply 143*0a86a4d1SLiu Ying - avcc-supply 144*0a86a4d1SLiu Ying - anvdd-supply 145*0a86a4d1SLiu Ying - apvdd-supply 146*0a86a4d1SLiu Ying 147*0a86a4d1SLiu YingunevaluatedProperties: false 148*0a86a4d1SLiu Ying 149*0a86a4d1SLiu Yingexamples: 150*0a86a4d1SLiu Ying - | 151*0a86a4d1SLiu Ying /* single-link LVDS input */ 152*0a86a4d1SLiu Ying #include <dt-bindings/gpio/gpio.h> 153*0a86a4d1SLiu Ying 154*0a86a4d1SLiu Ying i2c { 155*0a86a4d1SLiu Ying #address-cells = <1>; 156*0a86a4d1SLiu Ying #size-cells = <0>; 157*0a86a4d1SLiu Ying 158*0a86a4d1SLiu Ying hdmi@4c { 159*0a86a4d1SLiu Ying compatible = "ite,it6263"; 160*0a86a4d1SLiu Ying reg = <0x4c>; 161*0a86a4d1SLiu Ying data-mapping = "jeida-24"; 162*0a86a4d1SLiu Ying reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 163*0a86a4d1SLiu Ying ivdd-supply = <®_buck5>; 164*0a86a4d1SLiu Ying ovdd-supply = <®_vext_3v3>; 165*0a86a4d1SLiu Ying txavcc18-supply = <®_buck5>; 166*0a86a4d1SLiu Ying txavcc33-supply = <®_vext_3v3>; 167*0a86a4d1SLiu Ying pvcc1-supply = <®_buck5>; 168*0a86a4d1SLiu Ying pvcc2-supply = <®_buck5>; 169*0a86a4d1SLiu Ying avcc-supply = <®_vext_3v3>; 170*0a86a4d1SLiu Ying anvdd-supply = <®_buck5>; 171*0a86a4d1SLiu Ying apvdd-supply = <®_buck5>; 172*0a86a4d1SLiu Ying 173*0a86a4d1SLiu Ying ports { 174*0a86a4d1SLiu Ying #address-cells = <1>; 175*0a86a4d1SLiu Ying #size-cells = <0>; 176*0a86a4d1SLiu Ying 177*0a86a4d1SLiu Ying port@0 { 178*0a86a4d1SLiu Ying reg = <0>; 179*0a86a4d1SLiu Ying 180*0a86a4d1SLiu Ying it6263_lvds_link1: endpoint { 181*0a86a4d1SLiu Ying remote-endpoint = <&ldb_lvds_ch0>; 182*0a86a4d1SLiu Ying }; 183*0a86a4d1SLiu Ying }; 184*0a86a4d1SLiu Ying 185*0a86a4d1SLiu Ying port@2 { 186*0a86a4d1SLiu Ying reg = <2>; 187*0a86a4d1SLiu Ying 188*0a86a4d1SLiu Ying it6263_out: endpoint { 189*0a86a4d1SLiu Ying remote-endpoint = <&hdmi_in>; 190*0a86a4d1SLiu Ying }; 191*0a86a4d1SLiu Ying }; 192*0a86a4d1SLiu Ying }; 193*0a86a4d1SLiu Ying }; 194*0a86a4d1SLiu Ying }; 195*0a86a4d1SLiu Ying 196*0a86a4d1SLiu Ying - | 197*0a86a4d1SLiu Ying /* dual-link LVDS input */ 198*0a86a4d1SLiu Ying #include <dt-bindings/gpio/gpio.h> 199*0a86a4d1SLiu Ying 200*0a86a4d1SLiu Ying i2c { 201*0a86a4d1SLiu Ying #address-cells = <1>; 202*0a86a4d1SLiu Ying #size-cells = <0>; 203*0a86a4d1SLiu Ying 204*0a86a4d1SLiu Ying hdmi@4c { 205*0a86a4d1SLiu Ying compatible = "ite,it6263"; 206*0a86a4d1SLiu Ying reg = <0x4c>; 207*0a86a4d1SLiu Ying data-mapping = "jeida-24"; 208*0a86a4d1SLiu Ying reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 209*0a86a4d1SLiu Ying ivdd-supply = <®_buck5>; 210*0a86a4d1SLiu Ying ovdd-supply = <®_vext_3v3>; 211*0a86a4d1SLiu Ying txavcc18-supply = <®_buck5>; 212*0a86a4d1SLiu Ying txavcc33-supply = <®_vext_3v3>; 213*0a86a4d1SLiu Ying pvcc1-supply = <®_buck5>; 214*0a86a4d1SLiu Ying pvcc2-supply = <®_buck5>; 215*0a86a4d1SLiu Ying avcc-supply = <®_vext_3v3>; 216*0a86a4d1SLiu Ying anvdd-supply = <®_buck5>; 217*0a86a4d1SLiu Ying apvdd-supply = <®_buck5>; 218*0a86a4d1SLiu Ying 219*0a86a4d1SLiu Ying ports { 220*0a86a4d1SLiu Ying #address-cells = <1>; 221*0a86a4d1SLiu Ying #size-cells = <0>; 222*0a86a4d1SLiu Ying 223*0a86a4d1SLiu Ying port@0 { 224*0a86a4d1SLiu Ying reg = <0>; 225*0a86a4d1SLiu Ying dual-lvds-odd-pixels; 226*0a86a4d1SLiu Ying 227*0a86a4d1SLiu Ying it6263_lvds_link1_dual: endpoint { 228*0a86a4d1SLiu Ying remote-endpoint = <&ldb_lvds_ch0>; 229*0a86a4d1SLiu Ying }; 230*0a86a4d1SLiu Ying }; 231*0a86a4d1SLiu Ying 232*0a86a4d1SLiu Ying port@1 { 233*0a86a4d1SLiu Ying reg = <1>; 234*0a86a4d1SLiu Ying dual-lvds-even-pixels; 235*0a86a4d1SLiu Ying 236*0a86a4d1SLiu Ying it6263_lvds_link2_dual: endpoint { 237*0a86a4d1SLiu Ying remote-endpoint = <&ldb_lvds_ch1>; 238*0a86a4d1SLiu Ying }; 239*0a86a4d1SLiu Ying }; 240*0a86a4d1SLiu Ying 241*0a86a4d1SLiu Ying port@2 { 242*0a86a4d1SLiu Ying reg = <2>; 243*0a86a4d1SLiu Ying 244*0a86a4d1SLiu Ying it6263_out_dual: endpoint { 245*0a86a4d1SLiu Ying remote-endpoint = <&hdmi_in>; 246*0a86a4d1SLiu Ying }; 247*0a86a4d1SLiu Ying }; 248*0a86a4d1SLiu Ying }; 249*0a86a4d1SLiu Ying }; 250*0a86a4d1SLiu Ying }; 251