xref: /linux/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml (revision 7255fcc80d4b525cc10cfaaf7f485830d4ed2000) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX8MP DWC HDMI TX Encoder
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11
12description:
13  The i.MX8MP HDMI transmitter is a Synopsys DesignWare
14  HDMI 2.0a TX controller IP.
15
16allOf:
17  - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
18
19properties:
20  compatible:
21    enum:
22      - fsl,imx8mp-hdmi-tx
23
24  reg-io-width:
25    const: 1
26
27  clocks:
28    maxItems: 4
29
30  clock-names:
31    items:
32      - const: iahb
33      - const: isfr
34      - const: cec
35      - const: pix
36
37  power-domains:
38    maxItems: 1
39
40  ports:
41    $ref: /schemas/graph.yaml#/properties/ports
42
43    properties:
44      port@0:
45        $ref: /schemas/graph.yaml#/properties/port
46        description: Parallel RGB input port
47
48      port@1:
49        $ref: /schemas/graph.yaml#/properties/port
50        description: HDMI output port
51
52    required:
53      - port@0
54      - port@1
55
56required:
57  - compatible
58  - reg
59  - clocks
60  - clock-names
61  - interrupts
62  - power-domains
63  - ports
64
65unevaluatedProperties: false
66
67examples:
68  - |
69    #include <dt-bindings/clock/imx8mp-clock.h>
70    #include <dt-bindings/interrupt-controller/irq.h>
71    #include <dt-bindings/power/imx8mp-power.h>
72
73    hdmi@32fd8000 {
74        compatible = "fsl,imx8mp-hdmi-tx";
75        reg = <0x32fd8000 0x7eff>;
76        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
77        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
78                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
79                 <&clk IMX8MP_CLK_32K>,
80                 <&hdmi_tx_phy>;
81        clock-names = "iahb", "isfr", "cec", "pix";
82        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
83        reg-io-width = <1>;
84        ports {
85           #address-cells = <1>;
86           #size-cells = <0>;
87           port@0 {
88             reg = <0>;
89
90             hdmi_tx_from_pvi: endpoint {
91               remote-endpoint = <&pvi_to_hdmi_tx>;
92             };
93          };
94
95          port@1 {
96            reg = <1>;
97              hdmi_tx_out: endpoint {
98                remote-endpoint = <&hdmi0_con>;
99              };
100          };
101        };
102    };
103