19aab6601SXin Ji# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 29aab6601SXin Ji# Copyright 2019 Analogix Semiconductor, Inc. 39aab6601SXin Ji%YAML 1.2 49aab6601SXin Ji--- 59aab6601SXin Ji$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#" 69aab6601SXin Ji$schema: "http://devicetree.org/meta-schemas/core.yaml#" 79aab6601SXin Ji 89aab6601SXin Jititle: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter) 99aab6601SXin Ji 109aab6601SXin Jimaintainers: 119aab6601SXin Ji - Xin Ji <xji@analogixsemi.com> 129aab6601SXin Ji 139aab6601SXin Jidescription: | 149aab6601SXin Ji The ANX7625 is an ultra-low power 4K Mobile HD Transmitter 159aab6601SXin Ji designed for portable devices. 169aab6601SXin Ji 179aab6601SXin Jiproperties: 189aab6601SXin Ji compatible: 19*e5ace96fSKrzysztof Kozlowski const: analogix,anx7625 209aab6601SXin Ji 219aab6601SXin Ji reg: 229aab6601SXin Ji maxItems: 1 239aab6601SXin Ji 249aab6601SXin Ji interrupts: 259aab6601SXin Ji description: used for interrupt pin B8. 269aab6601SXin Ji maxItems: 1 279aab6601SXin Ji 289aab6601SXin Ji enable-gpios: 299aab6601SXin Ji description: used for power on chip control, POWER_EN pin D2. 309aab6601SXin Ji maxItems: 1 319aab6601SXin Ji 329aab6601SXin Ji reset-gpios: 339aab6601SXin Ji description: used for reset chip control, RESET_N pin B7. 349aab6601SXin Ji maxItems: 1 359aab6601SXin Ji 362f240cdbSHsin-Yi Wang vdd10-supply: 372f240cdbSHsin-Yi Wang description: Regulator that provides the supply 1.0V power. 382f240cdbSHsin-Yi Wang 392f240cdbSHsin-Yi Wang vdd18-supply: 402f240cdbSHsin-Yi Wang description: Regulator that provides the supply 1.8V power. 412f240cdbSHsin-Yi Wang 422f240cdbSHsin-Yi Wang vdd33-supply: 432f240cdbSHsin-Yi Wang description: Regulator that provides the supply 3.3V power. 442f240cdbSHsin-Yi Wang 45a43661e7SXin Ji analogix,lane0-swing: 46a43661e7SXin Ji $ref: /schemas/types.yaml#/definitions/uint8-array 47a43661e7SXin Ji minItems: 1 48a43661e7SXin Ji maxItems: 20 49a43661e7SXin Ji description: 50a43661e7SXin Ji an array of swing register setting for DP tx lane0 PHY. 51a43661e7SXin Ji Registers 0~9 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0, 52a43661e7SXin Ji Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2, 53a43661e7SXin Ji Swing1_Pre2, Swing0_Pre3, they are for [Boost control] and 54a43661e7SXin Ji [Swing control] setting. 55a43661e7SXin Ji Registers 0~9, bit 3:0 is [Boost control], these bits control 56a43661e7SXin Ji post cursor manual, increase the [Boost control] to increase 57a43661e7SXin Ji Pre-emphasis value. 58a43661e7SXin Ji Registers 0~9, bit 6:4 is [Swing control], these bits control 59a43661e7SXin Ji swing manual, increase [Swing control] setting to add Vp-p value 60a43661e7SXin Ji for each Swing, Pre. 61a43661e7SXin Ji Registers 10~19 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0, 62a43661e7SXin Ji Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2, 63a43661e7SXin Ji Swing1_Pre2, Swing0_Pre3, they are for [R select control] and 64a43661e7SXin Ji [R Termination control] setting. 65a43661e7SXin Ji Registers 10~19, bit 4:0 is [R select control], these bits are 66a43661e7SXin Ji compensation manual, increase it can enhance IO driven strength 67a43661e7SXin Ji and Vp-p. 68a43661e7SXin Ji Registers 10~19, bit 5:6 is [R termination control], these bits 69a43661e7SXin Ji adjust 50ohm impedance of DP tx termination. 00:55 ohm, 70a43661e7SXin Ji 01:50 ohm(default), 10:45 ohm, 11:40 ohm. 71a43661e7SXin Ji 72a43661e7SXin Ji analogix,lane1-swing: 73a43661e7SXin Ji $ref: /schemas/types.yaml#/definitions/uint8-array 74a43661e7SXin Ji minItems: 1 75a43661e7SXin Ji maxItems: 20 76a43661e7SXin Ji description: 77a43661e7SXin Ji an array of swing register setting for DP tx lane1 PHY. 78a43661e7SXin Ji DP TX lane1 swing register setting same with lane0 79a43661e7SXin Ji swing, please refer lane0-swing property description. 80a43661e7SXin Ji 81a43661e7SXin Ji analogix,audio-enable: 82a43661e7SXin Ji type: boolean 83a43661e7SXin Ji description: let the driver enable audio HDMI codec function or not. 84a43661e7SXin Ji 858f8dbb35SHsin-Yi Wang aux-bus: 868f8dbb35SHsin-Yi Wang $ref: /schemas/display/dp-aux-bus.yaml# 878f8dbb35SHsin-Yi Wang 889aab6601SXin Ji ports: 89b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/ports 909aab6601SXin Ji 919aab6601SXin Ji properties: 929aab6601SXin Ji port@0: 93a43661e7SXin Ji $ref: /schemas/graph.yaml#/$defs/port-base 94a43661e7SXin Ji unevaluatedProperties: false 959aab6601SXin Ji description: 960a61ef9cSXin Ji MIPI DSI/DPI input. 970a61ef9cSXin Ji 980a61ef9cSXin Ji properties: 990a61ef9cSXin Ji endpoint: 1000a61ef9cSXin Ji $ref: /schemas/media/video-interfaces.yaml# 1010a61ef9cSXin Ji type: object 1020a61ef9cSXin Ji additionalProperties: false 1030a61ef9cSXin Ji 1040a61ef9cSXin Ji properties: 1050a61ef9cSXin Ji remote-endpoint: true 1060a61ef9cSXin Ji 1070a61ef9cSXin Ji bus-type: 1080a61ef9cSXin Ji enum: [7] 1090a61ef9cSXin Ji default: 1 1100a61ef9cSXin Ji 1110a61ef9cSXin Ji data-lanes: true 1129aab6601SXin Ji 1139aab6601SXin Ji port@1: 114b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 1159aab6601SXin Ji description: 1169aab6601SXin Ji Video port for panel or connector. 1179aab6601SXin Ji 1189aab6601SXin Ji required: 1199aab6601SXin Ji - port@0 1209aab6601SXin Ji - port@1 1219aab6601SXin Ji 1229aab6601SXin Jirequired: 1239aab6601SXin Ji - compatible 1249aab6601SXin Ji - reg 1252f240cdbSHsin-Yi Wang - vdd10-supply 1262f240cdbSHsin-Yi Wang - vdd18-supply 1272f240cdbSHsin-Yi Wang - vdd33-supply 1289aab6601SXin Ji - ports 1299aab6601SXin Ji 1309aab6601SXin JiadditionalProperties: false 1319aab6601SXin Ji 1329aab6601SXin Jiexamples: 1339aab6601SXin Ji - | 1349aab6601SXin Ji #include <dt-bindings/gpio/gpio.h> 1359aab6601SXin Ji 13620a72af1SRob Herring i2c { 1379aab6601SXin Ji #address-cells = <1>; 1389aab6601SXin Ji #size-cells = <0>; 1399aab6601SXin Ji 1409aab6601SXin Ji encoder@58 { 1419aab6601SXin Ji compatible = "analogix,anx7625"; 1429aab6601SXin Ji reg = <0x58>; 1439aab6601SXin Ji enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; 1449aab6601SXin Ji reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; 1452f240cdbSHsin-Yi Wang vdd10-supply = <&pp1000_mipibrdg>; 1462f240cdbSHsin-Yi Wang vdd18-supply = <&pp1800_mipibrdg>; 1472f240cdbSHsin-Yi Wang vdd33-supply = <&pp3300_mipibrdg>; 148a43661e7SXin Ji analogix,audio-enable; 149a43661e7SXin Ji analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; 150a43661e7SXin Ji analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; 1519aab6601SXin Ji 1529aab6601SXin Ji ports { 1539aab6601SXin Ji #address-cells = <1>; 1549aab6601SXin Ji #size-cells = <0>; 1559aab6601SXin Ji 1569aab6601SXin Ji mipi2dp_bridge_in: port@0 { 1579aab6601SXin Ji reg = <0>; 1589aab6601SXin Ji anx7625_in: endpoint { 1599aab6601SXin Ji remote-endpoint = <&mipi_dsi>; 1600a61ef9cSXin Ji bus-type = <7>; 1610a61ef9cSXin Ji data-lanes = <0 1 2 3>; 1629aab6601SXin Ji }; 1639aab6601SXin Ji }; 1649aab6601SXin Ji 1659aab6601SXin Ji mipi2dp_bridge_out: port@1 { 1669aab6601SXin Ji reg = <1>; 1679aab6601SXin Ji anx7625_out: endpoint { 1689aab6601SXin Ji remote-endpoint = <&panel_in>; 1699aab6601SXin Ji }; 1709aab6601SXin Ji }; 1719aab6601SXin Ji }; 1728f8dbb35SHsin-Yi Wang 1738f8dbb35SHsin-Yi Wang aux-bus { 1748f8dbb35SHsin-Yi Wang panel { 1758f8dbb35SHsin-Yi Wang compatible = "innolux,n125hce-gn1"; 1768f8dbb35SHsin-Yi Wang power-supply = <&pp3300_disp_x>; 1778f8dbb35SHsin-Yi Wang backlight = <&backlight_lcd0>; 1788f8dbb35SHsin-Yi Wang 1798f8dbb35SHsin-Yi Wang port { 1808f8dbb35SHsin-Yi Wang panel_in: endpoint { 1818f8dbb35SHsin-Yi Wang remote-endpoint = <&anx7625_out>; 1828f8dbb35SHsin-Yi Wang }; 1838f8dbb35SHsin-Yi Wang }; 1848f8dbb35SHsin-Yi Wang }; 1858f8dbb35SHsin-Yi Wang }; 1869aab6601SXin Ji }; 1879aab6601SXin Ji }; 188