19aab6601SXin Ji# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 29aab6601SXin Ji# Copyright 2019 Analogix Semiconductor, Inc. 39aab6601SXin Ji%YAML 1.2 49aab6601SXin Ji--- 59aab6601SXin Ji$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#" 69aab6601SXin Ji$schema: "http://devicetree.org/meta-schemas/core.yaml#" 79aab6601SXin Ji 89aab6601SXin Jititle: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter) 99aab6601SXin Ji 109aab6601SXin Jimaintainers: 119aab6601SXin Ji - Xin Ji <xji@analogixsemi.com> 129aab6601SXin Ji 139aab6601SXin Jidescription: | 149aab6601SXin Ji The ANX7625 is an ultra-low power 4K Mobile HD Transmitter 159aab6601SXin Ji designed for portable devices. 169aab6601SXin Ji 179aab6601SXin Jiproperties: 189aab6601SXin Ji compatible: 199aab6601SXin Ji items: 209aab6601SXin Ji - const: analogix,anx7625 219aab6601SXin Ji 229aab6601SXin Ji reg: 239aab6601SXin Ji maxItems: 1 249aab6601SXin Ji 259aab6601SXin Ji interrupts: 269aab6601SXin Ji description: used for interrupt pin B8. 279aab6601SXin Ji maxItems: 1 289aab6601SXin Ji 299aab6601SXin Ji enable-gpios: 309aab6601SXin Ji description: used for power on chip control, POWER_EN pin D2. 319aab6601SXin Ji maxItems: 1 329aab6601SXin Ji 339aab6601SXin Ji reset-gpios: 349aab6601SXin Ji description: used for reset chip control, RESET_N pin B7. 359aab6601SXin Ji maxItems: 1 369aab6601SXin Ji 372f240cdbSHsin-Yi Wang vdd10-supply: 382f240cdbSHsin-Yi Wang description: Regulator that provides the supply 1.0V power. 392f240cdbSHsin-Yi Wang 402f240cdbSHsin-Yi Wang vdd18-supply: 412f240cdbSHsin-Yi Wang description: Regulator that provides the supply 1.8V power. 422f240cdbSHsin-Yi Wang 432f240cdbSHsin-Yi Wang vdd33-supply: 442f240cdbSHsin-Yi Wang description: Regulator that provides the supply 3.3V power. 452f240cdbSHsin-Yi Wang 46a43661e7SXin Ji analogix,lane0-swing: 47a43661e7SXin Ji $ref: /schemas/types.yaml#/definitions/uint8-array 48a43661e7SXin Ji minItems: 1 49a43661e7SXin Ji maxItems: 20 50a43661e7SXin Ji description: 51a43661e7SXin Ji an array of swing register setting for DP tx lane0 PHY. 52a43661e7SXin Ji Registers 0~9 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0, 53a43661e7SXin Ji Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2, 54a43661e7SXin Ji Swing1_Pre2, Swing0_Pre3, they are for [Boost control] and 55a43661e7SXin Ji [Swing control] setting. 56a43661e7SXin Ji Registers 0~9, bit 3:0 is [Boost control], these bits control 57a43661e7SXin Ji post cursor manual, increase the [Boost control] to increase 58a43661e7SXin Ji Pre-emphasis value. 59a43661e7SXin Ji Registers 0~9, bit 6:4 is [Swing control], these bits control 60a43661e7SXin Ji swing manual, increase [Swing control] setting to add Vp-p value 61a43661e7SXin Ji for each Swing, Pre. 62a43661e7SXin Ji Registers 10~19 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0, 63a43661e7SXin Ji Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2, 64a43661e7SXin Ji Swing1_Pre2, Swing0_Pre3, they are for [R select control] and 65a43661e7SXin Ji [R Termination control] setting. 66a43661e7SXin Ji Registers 10~19, bit 4:0 is [R select control], these bits are 67a43661e7SXin Ji compensation manual, increase it can enhance IO driven strength 68a43661e7SXin Ji and Vp-p. 69a43661e7SXin Ji Registers 10~19, bit 5:6 is [R termination control], these bits 70a43661e7SXin Ji adjust 50ohm impedance of DP tx termination. 00:55 ohm, 71a43661e7SXin Ji 01:50 ohm(default), 10:45 ohm, 11:40 ohm. 72a43661e7SXin Ji 73a43661e7SXin Ji analogix,lane1-swing: 74a43661e7SXin Ji $ref: /schemas/types.yaml#/definitions/uint8-array 75a43661e7SXin Ji minItems: 1 76a43661e7SXin Ji maxItems: 20 77a43661e7SXin Ji description: 78a43661e7SXin Ji an array of swing register setting for DP tx lane1 PHY. 79a43661e7SXin Ji DP TX lane1 swing register setting same with lane0 80a43661e7SXin Ji swing, please refer lane0-swing property description. 81a43661e7SXin Ji 82a43661e7SXin Ji analogix,audio-enable: 83a43661e7SXin Ji type: boolean 84a43661e7SXin Ji description: let the driver enable audio HDMI codec function or not. 85a43661e7SXin Ji 86*8f8dbb35SHsin-Yi Wang aux-bus: 87*8f8dbb35SHsin-Yi Wang $ref: /schemas/display/dp-aux-bus.yaml# 88*8f8dbb35SHsin-Yi Wang 899aab6601SXin Ji ports: 90b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/ports 919aab6601SXin Ji 929aab6601SXin Ji properties: 939aab6601SXin Ji port@0: 94a43661e7SXin Ji $ref: /schemas/graph.yaml#/$defs/port-base 95a43661e7SXin Ji unevaluatedProperties: false 969aab6601SXin Ji description: 97a43661e7SXin Ji MIPI DSI/DPI input. 98a43661e7SXin Ji 99a43661e7SXin Ji properties: 100a43661e7SXin Ji endpoint: 101a43661e7SXin Ji $ref: /schemas/media/video-interfaces.yaml# 102a43661e7SXin Ji type: object 103a43661e7SXin Ji additionalProperties: false 104a43661e7SXin Ji 105a43661e7SXin Ji properties: 106a43661e7SXin Ji remote-endpoint: true 107a43661e7SXin Ji 108a43661e7SXin Ji bus-type: 109a43661e7SXin Ji enum: [1, 5] 110a43661e7SXin Ji default: 1 111a43661e7SXin Ji 112a43661e7SXin Ji data-lanes: true 1139aab6601SXin Ji 1149aab6601SXin Ji port@1: 115b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 1169aab6601SXin Ji description: 1179aab6601SXin Ji Video port for panel or connector. 1189aab6601SXin Ji 1199aab6601SXin Ji required: 1209aab6601SXin Ji - port@0 1219aab6601SXin Ji - port@1 1229aab6601SXin Ji 1239aab6601SXin Jirequired: 1249aab6601SXin Ji - compatible 1259aab6601SXin Ji - reg 1262f240cdbSHsin-Yi Wang - vdd10-supply 1272f240cdbSHsin-Yi Wang - vdd18-supply 1282f240cdbSHsin-Yi Wang - vdd33-supply 1299aab6601SXin Ji - ports 1309aab6601SXin Ji 1319aab6601SXin JiadditionalProperties: false 1329aab6601SXin Ji 1339aab6601SXin Jiexamples: 1349aab6601SXin Ji - | 1359aab6601SXin Ji #include <dt-bindings/gpio/gpio.h> 1369aab6601SXin Ji 1379aab6601SXin Ji i2c0 { 1389aab6601SXin Ji #address-cells = <1>; 1399aab6601SXin Ji #size-cells = <0>; 1409aab6601SXin Ji 1419aab6601SXin Ji encoder@58 { 1429aab6601SXin Ji compatible = "analogix,anx7625"; 1439aab6601SXin Ji reg = <0x58>; 1449aab6601SXin Ji enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; 1459aab6601SXin Ji reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; 1462f240cdbSHsin-Yi Wang vdd10-supply = <&pp1000_mipibrdg>; 1472f240cdbSHsin-Yi Wang vdd18-supply = <&pp1800_mipibrdg>; 1482f240cdbSHsin-Yi Wang vdd33-supply = <&pp3300_mipibrdg>; 149a43661e7SXin Ji analogix,audio-enable; 150a43661e7SXin Ji analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; 151a43661e7SXin Ji analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; 1529aab6601SXin Ji 1539aab6601SXin Ji ports { 1549aab6601SXin Ji #address-cells = <1>; 1559aab6601SXin Ji #size-cells = <0>; 1569aab6601SXin Ji 1579aab6601SXin Ji mipi2dp_bridge_in: port@0 { 1589aab6601SXin Ji reg = <0>; 1599aab6601SXin Ji anx7625_in: endpoint { 1609aab6601SXin Ji remote-endpoint = <&mipi_dsi>; 161a43661e7SXin Ji bus-type = <5>; 162a43661e7SXin Ji data-lanes = <0 1 2 3>; 1639aab6601SXin Ji }; 1649aab6601SXin Ji }; 1659aab6601SXin Ji 1669aab6601SXin Ji mipi2dp_bridge_out: port@1 { 1679aab6601SXin Ji reg = <1>; 1689aab6601SXin Ji anx7625_out: endpoint { 1699aab6601SXin Ji remote-endpoint = <&panel_in>; 1709aab6601SXin Ji }; 1719aab6601SXin Ji }; 1729aab6601SXin Ji }; 173*8f8dbb35SHsin-Yi Wang 174*8f8dbb35SHsin-Yi Wang aux-bus { 175*8f8dbb35SHsin-Yi Wang panel { 176*8f8dbb35SHsin-Yi Wang compatible = "innolux,n125hce-gn1"; 177*8f8dbb35SHsin-Yi Wang power-supply = <&pp3300_disp_x>; 178*8f8dbb35SHsin-Yi Wang backlight = <&backlight_lcd0>; 179*8f8dbb35SHsin-Yi Wang 180*8f8dbb35SHsin-Yi Wang port { 181*8f8dbb35SHsin-Yi Wang panel_in: endpoint { 182*8f8dbb35SHsin-Yi Wang remote-endpoint = <&anx7625_out>; 183*8f8dbb35SHsin-Yi Wang }; 184*8f8dbb35SHsin-Yi Wang }; 185*8f8dbb35SHsin-Yi Wang }; 186*8f8dbb35SHsin-Yi Wang }; 1879aab6601SXin Ji }; 1889aab6601SXin Ji }; 189