xref: /linux/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml (revision bba2c3615bd6cfee7456d1130f2e6b01b3f4e9ba) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,eliza-inline-crypto-engine
17          - qcom,hawi-inline-crypto-engine
18          - qcom,kaanapali-inline-crypto-engine
19          - qcom,milos-inline-crypto-engine
20          - qcom,qcs8300-inline-crypto-engine
21          - qcom,sa8775p-inline-crypto-engine
22          - qcom,sc7180-inline-crypto-engine
23          - qcom,sc7280-inline-crypto-engine
24          - qcom,sm8450-inline-crypto-engine
25          - qcom,sm8550-inline-crypto-engine
26          - qcom,sm8650-inline-crypto-engine
27          - qcom,sm8750-inline-crypto-engine
28      - const: qcom,inline-crypto-engine
29
30  reg:
31    maxItems: 1
32
33  clocks:
34    minItems: 1
35    maxItems: 2
36
37  clock-names:
38    minItems: 1
39    items:
40      - const: core
41      - const: iface
42
43  power-domains:
44    maxItems: 1
45
46  operating-points-v2: true
47
48  opp-table:
49    type: object
50
51required:
52  - compatible
53  - reg
54  - clocks
55
56additionalProperties: false
57
58allOf:
59  - if:
60      properties:
61        compatible:
62          contains:
63            enum:
64              - qcom,eliza-inline-crypto-engine
65              - qcom,milos-inline-crypto-engine
66
67    then:
68      required:
69        - power-domains
70        - clock-names
71      properties:
72        clocks:
73          minItems: 2
74        clock-names:
75          minItems: 2
76
77examples:
78  - |
79    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
80
81    crypto@1d88000 {
82      compatible = "qcom,sm8550-inline-crypto-engine",
83                   "qcom,inline-crypto-engine";
84      reg = <0x01d88000 0x8000>;
85      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
86               <&gcc GCC_UFS_PHY_AHB_CLK>;
87      clock-names = "core",
88                    "iface";
89      power-domains = <&gcc UFS_PHY_GDSC>;
90
91      operating-points-v2 = <&ice_opp_table>;
92
93      ice_opp_table: opp-table {
94        compatible = "operating-points-v2";
95
96        opp-100000000 {
97          opp-hz = /bits/ 64 <100000000>;
98          required-opps = <&rpmhpd_opp_low_svs>;
99        };
100
101        opp-201500000 {
102          opp-hz = /bits/ 64 <201500000>;
103          required-opps = <&rpmhpd_opp_svs_l1>;
104        };
105
106        opp-403000000 {
107          opp-hz = /bits/ 64 <403000000>;
108          required-opps = <&rpmhpd_opp_nom>;
109        };
110      };
111    };
112...
113