xref: /linux/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml (revision 9d3c82be49130081392efc7fd769e7301675abcf) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,eliza-inline-crypto-engine
17          - qcom,hawi-inline-crypto-engine
18          - qcom,kaanapali-inline-crypto-engine
19          - qcom,maili-inline-crypto-engine
20          - qcom,milos-inline-crypto-engine
21          - qcom,nord-inline-crypto-engine
22          - qcom,qcs8300-inline-crypto-engine
23          - qcom,sa8775p-inline-crypto-engine
24          - qcom,sc7180-inline-crypto-engine
25          - qcom,sc7280-inline-crypto-engine
26          - qcom,shikra-inline-crypto-engine
27          - qcom,sm8450-inline-crypto-engine
28          - qcom,sm8550-inline-crypto-engine
29          - qcom,sm8650-inline-crypto-engine
30          - qcom,sm8750-inline-crypto-engine
31      - const: qcom,inline-crypto-engine
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    minItems: 1
38    maxItems: 2
39
40  clock-names:
41    minItems: 1
42    items:
43      - const: core
44      - const: iface
45
46  power-domains:
47    maxItems: 1
48
49  operating-points-v2: true
50
51  opp-table:
52    type: object
53
54required:
55  - compatible
56  - reg
57  - clocks
58
59additionalProperties: false
60
61# Do not extend the list.
62# Legacy SoCs are allowed for single clock.
63# New SoCs must provide both clocks and power domains.
64allOf:
65  - if:
66      not:
67        properties:
68          compatible:
69            contains:
70              enum:
71                - qcom,kaanapali-inline-crypto-engine
72                - qcom,qcs8300-inline-crypto-engine
73                - qcom,sa8775p-inline-crypto-engine
74                - qcom,sc7180-inline-crypto-engine
75                - qcom,sc7280-inline-crypto-engine
76                - qcom,sm8450-inline-crypto-engine
77                - qcom,sm8550-inline-crypto-engine
78                - qcom,sm8650-inline-crypto-engine
79                - qcom,sm8750-inline-crypto-engine
80
81    then:
82      required:
83        - power-domains
84        - clock-names
85      properties:
86        clocks:
87          minItems: 2
88        clock-names:
89          minItems: 2
90
91examples:
92  - |
93    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
94
95    crypto@1d88000 {
96      compatible = "qcom,sm8550-inline-crypto-engine",
97                   "qcom,inline-crypto-engine";
98      reg = <0x01d88000 0x8000>;
99      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
100               <&gcc GCC_UFS_PHY_AHB_CLK>;
101      clock-names = "core",
102                    "iface";
103      power-domains = <&gcc UFS_PHY_GDSC>;
104
105      operating-points-v2 = <&ice_opp_table>;
106
107      ice_opp_table: opp-table {
108        compatible = "operating-points-v2";
109
110        opp-100000000 {
111          opp-hz = /bits/ 64 <100000000>;
112          required-opps = <&rpmhpd_opp_low_svs>;
113        };
114
115        opp-201500000 {
116          opp-hz = /bits/ 64 <201500000>;
117          required-opps = <&rpmhpd_opp_svs_l1>;
118        };
119
120        opp-403000000 {
121          opp-hz = /bits/ 64 <403000000>;
122          required-opps = <&rpmhpd_opp_nom>;
123        };
124      };
125    };
126...
127