xref: /linux/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml (revision 6443f4f20bdae726fe01cf5946fba9742a0ffda6) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,eliza-inline-crypto-engine
17          - qcom,kaanapali-inline-crypto-engine
18          - qcom,milos-inline-crypto-engine
19          - qcom,qcs8300-inline-crypto-engine
20          - qcom,sa8775p-inline-crypto-engine
21          - qcom,sc7180-inline-crypto-engine
22          - qcom,sc7280-inline-crypto-engine
23          - qcom,sm8450-inline-crypto-engine
24          - qcom,sm8550-inline-crypto-engine
25          - qcom,sm8650-inline-crypto-engine
26          - qcom,sm8750-inline-crypto-engine
27      - const: qcom,inline-crypto-engine
28
29  reg:
30    maxItems: 1
31
32  clocks:
33    minItems: 1
34    maxItems: 2
35
36  clock-names:
37    minItems: 1
38    items:
39      - const: core
40      - const: iface
41
42  power-domains:
43    maxItems: 1
44
45  operating-points-v2: true
46
47  opp-table:
48    type: object
49
50required:
51  - compatible
52  - reg
53  - clocks
54
55additionalProperties: false
56
57allOf:
58  - if:
59      properties:
60        compatible:
61          contains:
62            enum:
63              - qcom,eliza-inline-crypto-engine
64              - qcom,milos-inline-crypto-engine
65
66    then:
67      required:
68        - power-domains
69        - clock-names
70      properties:
71        clocks:
72          minItems: 2
73        clock-names:
74          minItems: 2
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
79
80    crypto@1d88000 {
81      compatible = "qcom,sm8550-inline-crypto-engine",
82                   "qcom,inline-crypto-engine";
83      reg = <0x01d88000 0x8000>;
84      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
85               <&gcc GCC_UFS_PHY_AHB_CLK>;
86      clock-names = "core",
87                    "iface";
88      power-domains = <&gcc UFS_PHY_GDSC>;
89
90      operating-points-v2 = <&ice_opp_table>;
91
92      ice_opp_table: opp-table {
93        compatible = "operating-points-v2";
94
95        opp-100000000 {
96          opp-hz = /bits/ 64 <100000000>;
97          required-opps = <&rpmhpd_opp_low_svs>;
98        };
99
100        opp-201500000 {
101          opp-hz = /bits/ 64 <201500000>;
102          required-opps = <&rpmhpd_opp_svs_l1>;
103        };
104
105        opp-403000000 {
106          opp-hz = /bits/ 64 <403000000>;
107          required-opps = <&rpmhpd_opp_nom>;
108        };
109      };
110    };
111...
112