xref: /linux/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Keem Bay OCS HCU
8
9maintainers:
10  - Declan Murphy <declan.murphy@intel.com>
11  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
12
13description:
14  The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)
15  provides hardware-accelerated hashing and HMAC.
16
17properties:
18  compatible:
19    const: intel,keembay-ocs-hcu
20
21  reg:
22    maxItems: 1
23
24  interrupts:
25    maxItems: 1
26
27  clocks:
28    maxItems: 1
29
30required:
31  - compatible
32  - reg
33  - interrupts
34  - clocks
35
36additionalProperties: false
37
38examples:
39  - |
40    #include <dt-bindings/interrupt-controller/arm-gic.h>
41    crypto@3000b000 {
42      compatible = "intel,keembay-ocs-hcu";
43      reg = <0x3000b000 0x1000>;
44      interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
45      clocks = <&scmi_clk 94>;
46    };
47