1# SPDX-License-Identifier: GPL-2.0 2# Copyright (C) 2008-2011 Freescale Semiconductor Inc. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Freescale SEC 4 9 10maintainers: 11 - '"Horia Geantă" <horia.geanta@nxp.com>' 12 - Pankaj Gupta <pankaj.gupta@nxp.com> 13 - Gaurav Jain <gaurav.jain@nxp.com> 14 15description: | 16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator 17 Accelerator and Assurance Module (CAAM). 18 19 SEC 4 h/w can process requests from 2 types of sources. 20 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). 21 2. Job Rings (HW interface between cores & SEC 4 registers). 22 23 High Speed Data Path Configuration: 24 25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts 26 such as the P4080. The number of simultaneous dequeues the QI can make is 27 equal to the number of Descriptor Controller (DECO) engines in a particular 28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus 29 dequeue from 5 subportals simultaneously. 30 31 Job Ring Data Path Configuration: 32 33 Each JR is located on a separate 4k page, they may (or may not) be made visible 34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so 35 up to 4 JRs can be configured; and all 4 JRs process requests in parallel. 36 37properties: 38 compatible: 39 oneOf: 40 - items: 41 - enum: 42 - fsl,sec-v5.4 43 - fsl,sec-v6.0 44 - const: fsl,sec-v5.0 45 - const: fsl,sec-v4.0 46 - items: 47 - enum: 48 - fsl,imx6ul-caam 49 - fsl,imx8qm-caam 50 - fsl,imx8qxp-caam 51 - fsl,sec-v5.0 52 - const: fsl,sec-v4.0 53 - const: fsl,sec-v4.0 54 55 reg: 56 maxItems: 1 57 58 ranges: 59 maxItems: 1 60 61 '#address-cells': 62 enum: [1, 2] 63 64 '#size-cells': 65 enum: [1, 2] 66 67 clocks: 68 minItems: 1 69 maxItems: 4 70 71 clock-names: 72 minItems: 1 73 maxItems: 4 74 items: 75 enum: [mem, aclk, ipg, emi_slow] 76 77 dma-coherent: true 78 79 interrupts: 80 maxItems: 1 81 82 power-domains: 83 maxItems: 1 84 85 fsl,sec-era: 86 description: Defines the 'ERA' of the SEC device. 87 $ref: /schemas/types.yaml#/definitions/uint32 88 89patternProperties: 90 '^jr@[0-9a-f]+$': 91 type: object 92 additionalProperties: false 93 description: 94 Job Ring (JR) Node. Defines data processing interface to SEC 4 across the 95 peripheral bus for purposes of processing cryptographic descriptors. The 96 specified address range can be made visible to one (or more) cores. The 97 interrupt defined for this node is controlled within the address range of 98 this node. 99 100 properties: 101 compatible: 102 oneOf: 103 - items: 104 - const: fsl,sec-v6.0-job-ring 105 - const: fsl,sec-v5.2-job-ring 106 - const: fsl,sec-v5.0-job-ring 107 - const: fsl,sec-v4.4-job-ring 108 - const: fsl,sec-v4.0-job-ring 109 - items: 110 - const: fsl,sec-v5.4-job-ring 111 - const: fsl,sec-v5.0-job-ring 112 - const: fsl,sec-v4.0-job-ring 113 - items: 114 - enum: 115 - fsl,imx8qm-job-ring 116 - fsl,imx8qxp-job-ring 117 - fsl,sec-v5.0-job-ring 118 - const: fsl,sec-v4.0-job-ring 119 - const: fsl,sec-v4.0-job-ring 120 121 reg: 122 maxItems: 1 123 124 interrupts: 125 maxItems: 1 126 127 power-domains: 128 maxItems: 1 129 130 fsl,liodn: 131 description: 132 Specifies the LIODN to be used in conjunction with the ppid-to-liodn 133 table that specifies the PPID to LIODN mapping. Needed if the PAMU is 134 used. Value is a 12 bit value where value is a LIODN ID for this JR. 135 This property is normally set by boot firmware. 136 $ref: /schemas/types.yaml#/definitions/uint32-array 137 items: 138 - maximum: 0xfff 139 allOf: 140 - if: 141 properties: 142 compatible: 143 contains: 144 enum: 145 - fsl,imx8qm-job-ring 146 - fsl,imx8qxp-job-ring 147 then: 148 required: 149 - power-domains 150 else: 151 properties: 152 power-domains: false 153 154 '^rtic@[0-9a-f]+$': 155 type: object 156 additionalProperties: false 157 description: 158 Run Time Integrity Check (RTIC) Node. Defines a register space that 159 contains up to 5 sets of addresses and their lengths (sizes) that will be 160 checked at run time. After an initial hash result is calculated, these 161 addresses are checked by HW to monitor any change. If any memory is 162 modified, a Security Violation is triggered (see SNVS definition). 163 164 properties: 165 compatible: 166 oneOf: 167 - items: 168 - const: fsl,sec-v5.4-rtic 169 - const: fsl,sec-v5.0-rtic 170 - const: fsl,sec-v4.0-rtic 171 - const: fsl,sec-v4.0-rtic 172 173 reg: 174 items: 175 - description: RTIC control and status register space. 176 - description: RTIC recoverable error indication register space. 177 minItems: 1 178 179 ranges: 180 maxItems: 1 181 182 interrupts: 183 maxItems: 1 184 185 '#address-cells': 186 const: 1 187 188 '#size-cells': 189 const: 1 190 191 patternProperties: 192 '^rtic-[a-z]@[0-9a-f]+$': 193 type: object 194 additionalProperties: false 195 description: 196 Run Time Integrity Check (RTIC) Memory Node defines individual RTIC 197 memory regions that are used to perform run-time integrity check of 198 memory areas that should not modified. The node defines a register 199 that contains the memory address & length (combined) and a second 200 register that contains the hash result in big endian format. 201 202 properties: 203 compatible: 204 oneOf: 205 - items: 206 - const: fsl,sec-v5.4-rtic-memory 207 - const: fsl,sec-v5.0-rtic-memory 208 - const: fsl,sec-v4.0-rtic-memory 209 - const: fsl,sec-v4.0-rtic-memory 210 211 reg: 212 items: 213 - description: RTIC memory address 214 - description: RTIC hash result 215 216 fsl,liodn: 217 description: 218 Specifies the LIODN to be used in conjunction with the 219 ppid-to-liodn table that specifies the PPID to LIODN mapping. 220 Needed if the PAMU is used. Value is a 12 bit value where value 221 is a LIODN ID for this JR. This property is normally set by boot 222 firmware. 223 $ref: /schemas/types.yaml#/definitions/uint32-array 224 items: 225 - maximum: 0xfff 226 227 fsl,rtic-region: 228 description: 229 Specifies the HW address (36 bit address) for this region 230 followed by the length of the HW partition to be checked; 231 the address is represented as a 64 bit quantity followed 232 by a 32 bit length. 233 $ref: /schemas/types.yaml#/definitions/uint32-array 234 235required: 236 - compatible 237 - reg 238 - ranges 239 240if: 241 properties: 242 compatible: 243 contains: 244 enum: 245 - fsl,imx8qm-caam 246 - fsl,imx8qxp-caam 247then: 248 required: 249 - power-domains 250else: 251 properties: 252 power-domains: false 253 254additionalProperties: false 255 256examples: 257 - | 258 crypto@300000 { 259 compatible = "fsl,sec-v4.0"; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 reg = <0x300000 0x10000>; 263 ranges = <0 0x300000 0x10000>; 264 interrupts = <92 2>; 265 266 jr@1000 { 267 compatible = "fsl,sec-v4.0-job-ring"; 268 reg = <0x1000 0x1000>; 269 interrupts = <88 2>; 270 }; 271 272 jr@2000 { 273 compatible = "fsl,sec-v4.0-job-ring"; 274 reg = <0x2000 0x1000>; 275 interrupts = <89 2>; 276 }; 277 278 jr@3000 { 279 compatible = "fsl,sec-v4.0-job-ring"; 280 reg = <0x3000 0x1000>; 281 interrupts = <90 2>; 282 }; 283 284 jr@4000 { 285 compatible = "fsl,sec-v4.0-job-ring"; 286 reg = <0x4000 0x1000>; 287 interrupts = <91 2>; 288 }; 289 290 rtic@6000 { 291 compatible = "fsl,sec-v4.0-rtic"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 reg = <0x6000 0x100>; 295 ranges = <0x0 0x6100 0xe00>; 296 297 rtic-a@0 { 298 compatible = "fsl,sec-v4.0-rtic-memory"; 299 reg = <0x00 0x20>, <0x100 0x80>; 300 }; 301 302 rtic-b@20 { 303 compatible = "fsl,sec-v4.0-rtic-memory"; 304 reg = <0x20 0x20>, <0x200 0x80>; 305 }; 306 307 rtic-c@40 { 308 compatible = "fsl,sec-v4.0-rtic-memory"; 309 reg = <0x40 0x20>, <0x300 0x80>; 310 }; 311 312 rtic-d@60 { 313 compatible = "fsl,sec-v4.0-rtic-memory"; 314 reg = <0x60 0x20>, <0x500 0x80>; 315 }; 316 }; 317 }; 318... 319