xref: /linux/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
9
10maintainers:
11  - Tudor Ambarus <tudor.ambarus@linaro.org>
12
13properties:
14  compatible:
15    oneOf:
16      - const: atmel,at91sam9g46-sha
17      - items:
18          - enum:
19              - microchip,sam9x7-sha
20              - microchip,sama7d65-sha
21          - const: atmel,at91sam9g46-sha
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  clock-names:
33    const: sha_clk
34
35  dmas:
36    maxItems: 1
37    description: TX DMA Channel
38
39  dma-names:
40    const: tx
41
42required:
43  - compatible
44  - reg
45  - interrupts
46  - clocks
47  - clock-names
48
49additionalProperties: false
50
51examples:
52  - |
53    #include <dt-bindings/interrupt-controller/irq.h>
54    #include <dt-bindings/interrupt-controller/arm-gic.h>
55    #include <dt-bindings/clock/at91.h>
56    #include <dt-bindings/dma/at91.h>
57
58    sha: crypto@e1814000 {
59      compatible = "atmel,at91sam9g46-sha";
60      reg = <0xe1814000 0x100>;
61      interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
62      clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
63      clock-names = "sha_clk";
64      dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
65      dma-names = "tx";
66    };
67