xref: /linux/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml (revision 8ca4fc323d2e4ab9dabbdd57633af40b0c7e6af9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator
9
10maintainers:
11  - Tudor Ambarus <tudor.ambarus@microchip.com>
12
13properties:
14  compatible:
15    const: atmel,at91sam9g46-aes
16
17  reg:
18    maxItems: 1
19
20  interrupts:
21    maxItems: 1
22
23  clocks:
24    maxItems: 1
25
26  clock-names:
27    const: aes_clk
28
29  dmas:
30    items:
31      - description: TX DMA Channel
32      - description: RX DMA Channel
33
34  dma-names:
35    items:
36      - const: tx
37      - const: rx
38
39required:
40  - compatible
41  - reg
42  - interrupts
43  - clocks
44  - clock-names
45  - dmas
46  - dma-names
47
48additionalProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/interrupt-controller/irq.h>
53    #include <dt-bindings/interrupt-controller/arm-gic.h>
54    #include <dt-bindings/clock/at91.h>
55    #include <dt-bindings/dma/at91.h>
56
57    aes: crypto@e1810000 {
58      compatible = "atmel,at91sam9g46-aes";
59      reg = <0xe1810000 0x100>;
60      interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
61      clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
62      clock-names = "aes_clk";
63      dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
64             <&dma0 AT91_XDMAC_DT_PERID(2)>;
65      dma-names = "tx", "rx";
66    };
67