1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. NVMEM CPUFreq 8 9maintainers: 10 - Ilia Lin <ilia.lin@kernel.org> 11 12description: | 13 In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply 14 voltage is dynamically configured by Core Power Reduction (CPR) depending on 15 current CPU frequency and efuse values. 16 CPR provides a power domain with multiple levels that are selected depending 17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level 18 according to the required OPPs defined in the CPU OPP tables. 19 20 For old implementation efuses are parsed to select the correct opp table and 21 voltage and CPR is not supported/used. 22 23select: 24 properties: 25 compatible: 26 contains: 27 enum: 28 - qcom,apq8064 29 - qcom,apq8096 30 - qcom,ipq5332 31 - qcom,ipq8064 32 - qcom,ipq8074 33 - qcom,ipq9574 34 - qcom,msm8939 35 - qcom,msm8960 36 - qcom,msm8974 37 - qcom,msm8996 38 - qcom,qcs404 39 required: 40 - compatible 41 42patternProperties: 43 '^opp-table(-[a-z0-9]+)?$': 44 allOf: 45 - if: 46 properties: 47 compatible: 48 const: operating-points-v2-kryo-cpu 49 then: 50 $ref: /schemas/opp/opp-v2-kryo-cpu.yaml# 51 52 - if: 53 properties: 54 compatible: 55 const: operating-points-v2-qcom-level 56 then: 57 $ref: /schemas/opp/opp-v2-qcom-level.yaml# 58 59 unevaluatedProperties: false 60 61allOf: 62 - if: 63 properties: 64 compatible: 65 contains: 66 enum: 67 - qcom,qcs404 68 69 then: 70 properties: 71 cpus: 72 type: object 73 74 patternProperties: 75 '^cpu@[0-9a-f]+$': 76 type: object 77 78 properties: 79 power-domains: 80 maxItems: 1 81 82 power-domain-names: 83 items: 84 - const: cpr 85 86 required: 87 - power-domains 88 - power-domain-names 89 90 patternProperties: 91 '^opp-table(-[a-z0-9]+)?$': 92 if: 93 properties: 94 compatible: 95 const: operating-points-v2-kryo-cpu 96 then: 97 patternProperties: 98 '^opp-?[0-9]+$': 99 required: 100 - required-opps 101 102additionalProperties: true 103 104examples: 105 - | 106 / { 107 model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; 108 compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 112 cpus { 113 #address-cells = <1>; 114 #size-cells = <0>; 115 116 CPU0: cpu@100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x100>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0>; 122 next-level-cache = <&L2_0>; 123 #cooling-cells = <2>; 124 clocks = <&apcs_glb>; 125 operating-points-v2 = <&cpu_opp_table>; 126 power-domains = <&cpr>; 127 power-domain-names = "cpr"; 128 }; 129 130 CPU1: cpu@101 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53"; 133 reg = <0x101>; 134 enable-method = "psci"; 135 cpu-idle-states = <&CPU_SLEEP_0>; 136 next-level-cache = <&L2_0>; 137 #cooling-cells = <2>; 138 clocks = <&apcs_glb>; 139 operating-points-v2 = <&cpu_opp_table>; 140 power-domains = <&cpr>; 141 power-domain-names = "cpr"; 142 }; 143 144 CPU2: cpu@102 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a53"; 147 reg = <0x102>; 148 enable-method = "psci"; 149 cpu-idle-states = <&CPU_SLEEP_0>; 150 next-level-cache = <&L2_0>; 151 #cooling-cells = <2>; 152 clocks = <&apcs_glb>; 153 operating-points-v2 = <&cpu_opp_table>; 154 power-domains = <&cpr>; 155 power-domain-names = "cpr"; 156 }; 157 158 CPU3: cpu@103 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a53"; 161 reg = <0x103>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0>; 164 next-level-cache = <&L2_0>; 165 #cooling-cells = <2>; 166 clocks = <&apcs_glb>; 167 operating-points-v2 = <&cpu_opp_table>; 168 power-domains = <&cpr>; 169 power-domain-names = "cpr"; 170 }; 171 }; 172 173 cpu_opp_table: opp-table-cpu { 174 compatible = "operating-points-v2-kryo-cpu"; 175 opp-shared; 176 177 opp-1094400000 { 178 opp-hz = /bits/ 64 <1094400000>; 179 required-opps = <&cpr_opp1>; 180 }; 181 opp-1248000000 { 182 opp-hz = /bits/ 64 <1248000000>; 183 required-opps = <&cpr_opp2>; 184 }; 185 opp-1401600000 { 186 opp-hz = /bits/ 64 <1401600000>; 187 required-opps = <&cpr_opp3>; 188 }; 189 }; 190 191 cpr_opp_table: opp-table-cpr { 192 compatible = "operating-points-v2-qcom-level"; 193 194 cpr_opp1: opp1 { 195 opp-level = <1>; 196 qcom,opp-fuse-level = <1>; 197 }; 198 cpr_opp2: opp2 { 199 opp-level = <2>; 200 qcom,opp-fuse-level = <2>; 201 }; 202 cpr_opp3: opp3 { 203 opp-level = <3>; 204 qcom,opp-fuse-level = <3>; 205 }; 206 }; 207 }; 208