1*42099322SDeepak SikriSPEAr cpufreq driver 2*42099322SDeepak Sikri------------------- 3*42099322SDeepak Sikri 4*42099322SDeepak SikriSPEAr SoC cpufreq driver for CPU frequency scaling. 5*42099322SDeepak SikriIt supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems 6*42099322SDeepak Sikriwhich share clock across all CPUs. 7*42099322SDeepak Sikri 8*42099322SDeepak SikriRequired properties: 9*42099322SDeepak Sikri- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the 10*42099322SDeepak Sikri increasing order. 11*42099322SDeepak Sikri 12*42099322SDeepak SikriOptional properties: 13*42099322SDeepak Sikri- clock-latency: Specify the possible maximum transition latency for clock, in 14*42099322SDeepak Sikri unit of nanoseconds. 15*42099322SDeepak Sikri 16*42099322SDeepak SikriBoth required and optional properties listed above must be defined under node 17*42099322SDeepak Sikri/cpus/cpu@0. 18*42099322SDeepak Sikri 19*42099322SDeepak SikriExamples: 20*42099322SDeepak Sikri-------- 21*42099322SDeepak Sikricpus { 22*42099322SDeepak Sikri 23*42099322SDeepak Sikri <...> 24*42099322SDeepak Sikri 25*42099322SDeepak Sikri cpu@0 { 26*42099322SDeepak Sikri compatible = "arm,cortex-a9"; 27*42099322SDeepak Sikri reg = <0>; 28*42099322SDeepak Sikri 29*42099322SDeepak Sikri <...> 30*42099322SDeepak Sikri 31*42099322SDeepak Sikri cpufreq_tbl = < 166000 32*42099322SDeepak Sikri 200000 33*42099322SDeepak Sikri 250000 34*42099322SDeepak Sikri 300000 35*42099322SDeepak Sikri 400000 36*42099322SDeepak Sikri 500000 37*42099322SDeepak Sikri 600000 >; 38*42099322SDeepak Sikri }; 39*42099322SDeepak Sikri 40*42099322SDeepak Sikri <...> 41*42099322SDeepak Sikri 42*42099322SDeepak Sikri}; 43