xref: /linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,sc7180-cpufreq-hw
26              - qcom,sc8180x-cpufreq-hw
27              - qcom,sdm670-cpufreq-hw
28              - qcom,sdm845-cpufreq-hw
29              - qcom,sm6115-cpufreq-hw
30              - qcom,sm6350-cpufreq-hw
31              - qcom,sm8150-cpufreq-hw
32          - const: qcom,cpufreq-hw
33
34      - description: v2 of CPUFREQ HW (EPSS)
35        items:
36          - enum:
37              - qcom,qdu1000-cpufreq-epss
38              - qcom,sa8255p-cpufreq-epss
39              - qcom,sa8775p-cpufreq-epss
40              - qcom,sar2130p-cpufreq-epss
41              - qcom,sc7280-cpufreq-epss
42              - qcom,sc8280xp-cpufreq-epss
43              - qcom,sdx75-cpufreq-epss
44              - qcom,sm4450-cpufreq-epss
45              - qcom,sm6375-cpufreq-epss
46              - qcom,sm8250-cpufreq-epss
47              - qcom,sm8350-cpufreq-epss
48              - qcom,sm8450-cpufreq-epss
49              - qcom,sm8550-cpufreq-epss
50              - qcom,sm8650-cpufreq-epss
51          - const: qcom,cpufreq-epss
52
53  reg:
54    minItems: 1
55    items:
56      - description: Frequency domain 0 register region
57      - description: Frequency domain 1 register region
58      - description: Frequency domain 2 register region
59      - description: Frequency domain 3 register region
60
61  reg-names:
62    minItems: 1
63    items:
64      - const: freq-domain0
65      - const: freq-domain1
66      - const: freq-domain2
67      - const: freq-domain3
68
69  clocks:
70    items:
71      - description: XO Clock
72      - description: GPLL0 Clock
73
74  clock-names:
75    items:
76      - const: xo
77      - const: alternate
78
79  interrupts:
80    minItems: 1
81    maxItems: 4
82
83  interrupt-names:
84    minItems: 1
85    items:
86      - const: dcvsh-irq-0
87      - const: dcvsh-irq-1
88      - const: dcvsh-irq-2
89      - const: dcvsh-irq-3
90
91  '#freq-domain-cells':
92    const: 1
93
94  '#clock-cells':
95    const: 1
96
97required:
98  - compatible
99  - reg
100  - clocks
101  - clock-names
102  - '#freq-domain-cells'
103
104additionalProperties: false
105
106allOf:
107  - if:
108      properties:
109        compatible:
110          contains:
111            enum:
112              - qcom,qcm2290-cpufreq-hw
113              - qcom,sar2130p-cpufreq-epss
114    then:
115      properties:
116        reg:
117          minItems: 1
118          maxItems: 1
119
120        reg-names:
121          minItems: 1
122          maxItems: 1
123
124        interrupts:
125          minItems: 1
126          maxItems: 1
127
128        interrupt-names:
129          minItems: 1
130
131  - if:
132      properties:
133        compatible:
134          contains:
135            enum:
136              - qcom,qdu1000-cpufreq-epss
137              - qcom,sa8255p-cpufreq-epss
138              - qcom,sc7180-cpufreq-hw
139              - qcom,sc8180x-cpufreq-hw
140              - qcom,sc8280xp-cpufreq-epss
141              - qcom,sdm670-cpufreq-hw
142              - qcom,sdm845-cpufreq-hw
143              - qcom,sm4450-cpufreq-epss
144              - qcom,sm6115-cpufreq-hw
145              - qcom,sm6350-cpufreq-hw
146              - qcom,sm6375-cpufreq-epss
147    then:
148      properties:
149        reg:
150          minItems: 2
151          maxItems: 2
152
153        reg-names:
154          minItems: 2
155          maxItems: 2
156
157        interrupts:
158          minItems: 2
159          maxItems: 2
160
161        interrupt-names:
162          minItems: 2
163
164  - if:
165      properties:
166        compatible:
167          contains:
168            enum:
169              - qcom,sc7280-cpufreq-epss
170              - qcom,sm8250-cpufreq-epss
171              - qcom,sm8350-cpufreq-epss
172              - qcom,sm8450-cpufreq-epss
173              - qcom,sm8550-cpufreq-epss
174    then:
175      properties:
176        reg:
177          minItems: 3
178          maxItems: 3
179
180        reg-names:
181          minItems: 3
182          maxItems: 3
183
184        interrupts:
185          minItems: 3
186          maxItems: 3
187
188        interrupt-names:
189          minItems: 3
190
191  - if:
192      properties:
193        compatible:
194          contains:
195            enum:
196              - qcom,sm8150-cpufreq-hw
197    then:
198      properties:
199        reg:
200          minItems: 3
201          maxItems: 3
202
203        reg-names:
204          minItems: 3
205          maxItems: 3
206
207        # On some SoCs the Prime core shares the LMH irq with Big cores
208        interrupts:
209          minItems: 2
210          maxItems: 2
211
212        interrupt-names:
213          minItems: 2
214
215
216examples:
217  - |
218    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
219    #include <dt-bindings/clock/qcom,rpmh.h>
220
221    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
222    // switch DCVS state together.
223    cpus {
224      #address-cells = <2>;
225      #size-cells = <0>;
226
227      CPU0: cpu@0 {
228        device_type = "cpu";
229        compatible = "qcom,kryo385";
230        reg = <0x0 0x0>;
231        enable-method = "psci";
232        next-level-cache = <&L2_0>;
233        qcom,freq-domain = <&cpufreq_hw 0>;
234        clocks = <&cpufreq_hw 0>;
235        L2_0: l2-cache {
236          compatible = "cache";
237          cache-unified;
238          cache-level = <2>;
239          next-level-cache = <&L3_0>;
240          L3_0: l3-cache {
241            compatible = "cache";
242            cache-unified;
243            cache-level = <3>;
244          };
245        };
246      };
247
248      CPU1: cpu@100 {
249        device_type = "cpu";
250        compatible = "qcom,kryo385";
251        reg = <0x0 0x100>;
252        enable-method = "psci";
253        next-level-cache = <&L2_100>;
254        qcom,freq-domain = <&cpufreq_hw 0>;
255        clocks = <&cpufreq_hw 0>;
256        L2_100: l2-cache {
257          compatible = "cache";
258          cache-unified;
259          cache-level = <2>;
260          next-level-cache = <&L3_0>;
261        };
262      };
263
264      CPU2: cpu@200 {
265        device_type = "cpu";
266        compatible = "qcom,kryo385";
267        reg = <0x0 0x200>;
268        enable-method = "psci";
269        next-level-cache = <&L2_200>;
270        qcom,freq-domain = <&cpufreq_hw 0>;
271        clocks = <&cpufreq_hw 0>;
272        L2_200: l2-cache {
273          compatible = "cache";
274          cache-unified;
275          cache-level = <2>;
276          next-level-cache = <&L3_0>;
277        };
278      };
279
280      CPU3: cpu@300 {
281        device_type = "cpu";
282        compatible = "qcom,kryo385";
283        reg = <0x0 0x300>;
284        enable-method = "psci";
285        next-level-cache = <&L2_300>;
286        qcom,freq-domain = <&cpufreq_hw 0>;
287        clocks = <&cpufreq_hw 0>;
288        L2_300: l2-cache {
289          compatible = "cache";
290          cache-unified;
291          cache-level = <2>;
292          next-level-cache = <&L3_0>;
293        };
294      };
295
296      CPU4: cpu@400 {
297        device_type = "cpu";
298        compatible = "qcom,kryo385";
299        reg = <0x0 0x400>;
300        enable-method = "psci";
301        next-level-cache = <&L2_400>;
302        qcom,freq-domain = <&cpufreq_hw 1>;
303        clocks = <&cpufreq_hw 1>;
304        L2_400: l2-cache {
305          compatible = "cache";
306          cache-unified;
307          cache-level = <2>;
308          next-level-cache = <&L3_0>;
309        };
310      };
311
312      CPU5: cpu@500 {
313        device_type = "cpu";
314        compatible = "qcom,kryo385";
315        reg = <0x0 0x500>;
316        enable-method = "psci";
317        next-level-cache = <&L2_500>;
318        qcom,freq-domain = <&cpufreq_hw 1>;
319        clocks = <&cpufreq_hw 1>;
320        L2_500: l2-cache {
321          compatible = "cache";
322          cache-unified;
323          cache-level = <2>;
324          next-level-cache = <&L3_0>;
325        };
326      };
327
328      CPU6: cpu@600 {
329        device_type = "cpu";
330        compatible = "qcom,kryo385";
331        reg = <0x0 0x600>;
332        enable-method = "psci";
333        next-level-cache = <&L2_600>;
334        qcom,freq-domain = <&cpufreq_hw 1>;
335        clocks = <&cpufreq_hw 1>;
336        L2_600: l2-cache {
337          compatible = "cache";
338          cache-unified;
339          cache-level = <2>;
340          next-level-cache = <&L3_0>;
341        };
342      };
343
344      CPU7: cpu@700 {
345        device_type = "cpu";
346        compatible = "qcom,kryo385";
347        reg = <0x0 0x700>;
348        enable-method = "psci";
349        next-level-cache = <&L2_700>;
350        qcom,freq-domain = <&cpufreq_hw 1>;
351        clocks = <&cpufreq_hw 1>;
352        L2_700: l2-cache {
353          compatible = "cache";
354          cache-unified;
355          cache-level = <2>;
356          next-level-cache = <&L3_0>;
357        };
358      };
359    };
360
361    soc {
362      #address-cells = <1>;
363      #size-cells = <1>;
364
365      cpufreq@17d43000 {
366        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
367        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
368        reg-names = "freq-domain0", "freq-domain1";
369
370        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
371        clock-names = "xo", "alternate";
372
373        #freq-domain-cells = <1>;
374        #clock-cells = <1>;
375      };
376    };
377...
378