xref: /linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml (revision 6f7e6393d1ce636bb7ec77a7fe7b77458fddf701) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,qcs615-cpufreq-hw
26              - qcom,sc7180-cpufreq-hw
27              - qcom,sc8180x-cpufreq-hw
28              - qcom,sdm670-cpufreq-hw
29              - qcom,sdm845-cpufreq-hw
30              - qcom,sm6115-cpufreq-hw
31              - qcom,sm6350-cpufreq-hw
32              - qcom,sm8150-cpufreq-hw
33          - const: qcom,cpufreq-hw
34
35      - description: v2 of CPUFREQ HW (EPSS)
36        items:
37          - enum:
38              - qcom,milos-cpufreq-epss
39              - qcom,qcs8300-cpufreq-epss
40              - qcom,qdu1000-cpufreq-epss
41              - qcom,sa8255p-cpufreq-epss
42              - qcom,sa8775p-cpufreq-epss
43              - qcom,sar2130p-cpufreq-epss
44              - qcom,sc7280-cpufreq-epss
45              - qcom,sc8280xp-cpufreq-epss
46              - qcom,sdx75-cpufreq-epss
47              - qcom,sm4450-cpufreq-epss
48              - qcom,sm6375-cpufreq-epss
49              - qcom,sm8250-cpufreq-epss
50              - qcom,sm8350-cpufreq-epss
51              - qcom,sm8450-cpufreq-epss
52              - qcom,sm8550-cpufreq-epss
53              - qcom,sm8650-cpufreq-epss
54          - const: qcom,cpufreq-epss
55
56  reg:
57    minItems: 1
58    items:
59      - description: Frequency domain 0 register region
60      - description: Frequency domain 1 register region
61      - description: Frequency domain 2 register region
62      - description: Frequency domain 3 register region
63
64  reg-names:
65    minItems: 1
66    items:
67      - const: freq-domain0
68      - const: freq-domain1
69      - const: freq-domain2
70      - const: freq-domain3
71
72  clocks:
73    items:
74      - description: XO Clock
75      - description: GPLL0 Clock
76
77  clock-names:
78    items:
79      - const: xo
80      - const: alternate
81
82  interrupts:
83    minItems: 1
84    maxItems: 4
85
86  interrupt-names:
87    minItems: 1
88    items:
89      - const: dcvsh-irq-0
90      - const: dcvsh-irq-1
91      - const: dcvsh-irq-2
92      - const: dcvsh-irq-3
93
94  '#freq-domain-cells':
95    const: 1
96
97  '#clock-cells':
98    const: 1
99
100required:
101  - compatible
102  - reg
103  - clocks
104  - clock-names
105  - '#freq-domain-cells'
106
107additionalProperties: false
108
109allOf:
110  - if:
111      properties:
112        compatible:
113          contains:
114            enum:
115              - qcom,qcm2290-cpufreq-hw
116              - qcom,sar2130p-cpufreq-epss
117              - qcom,sdx75-cpufreq-epss
118    then:
119      properties:
120        reg:
121          maxItems: 1
122
123        reg-names:
124          maxItems: 1
125
126        interrupts:
127          maxItems: 1
128
129        interrupt-names:
130          maxItems: 1
131
132  - if:
133      properties:
134        compatible:
135          contains:
136            enum:
137              - qcom,qcs615-cpufreq-hw
138              - qcom,qdu1000-cpufreq-epss
139              - qcom,sa8255p-cpufreq-epss
140              - qcom,sa8775p-cpufreq-epss
141              - qcom,sc7180-cpufreq-hw
142              - qcom,sc8180x-cpufreq-hw
143              - qcom,sc8280xp-cpufreq-epss
144              - qcom,sdm670-cpufreq-hw
145              - qcom,sdm845-cpufreq-hw
146              - qcom,sm4450-cpufreq-epss
147              - qcom,sm6115-cpufreq-hw
148              - qcom,sm6350-cpufreq-hw
149              - qcom,sm6375-cpufreq-epss
150    then:
151      properties:
152        reg:
153          minItems: 2
154          maxItems: 2
155
156        reg-names:
157          minItems: 2
158          maxItems: 2
159
160        interrupts:
161          minItems: 2
162          maxItems: 2
163
164        interrupt-names:
165          minItems: 2
166          maxItems: 2
167
168  - if:
169      properties:
170        compatible:
171          contains:
172            enum:
173              - qcom,milos-cpufreq-epss
174              - qcom,qcs8300-cpufreq-epss
175              - qcom,sc7280-cpufreq-epss
176              - qcom,sm8250-cpufreq-epss
177              - qcom,sm8350-cpufreq-epss
178              - qcom,sm8450-cpufreq-epss
179              - qcom,sm8550-cpufreq-epss
180    then:
181      properties:
182        reg:
183          minItems: 3
184          maxItems: 3
185
186        reg-names:
187          minItems: 3
188          maxItems: 3
189
190        interrupts:
191          minItems: 3
192          maxItems: 3
193
194        interrupt-names:
195          minItems: 3
196          maxItems: 3
197
198  - if:
199      properties:
200        compatible:
201          contains:
202            enum:
203              - qcom,sm8150-cpufreq-hw
204    then:
205      properties:
206        reg:
207          minItems: 3
208          maxItems: 3
209
210        reg-names:
211          minItems: 3
212          maxItems: 3
213
214        # On some SoCs the Prime core shares the LMH irq with Big cores
215        interrupts:
216          minItems: 2
217          maxItems: 2
218
219        interrupt-names:
220          minItems: 2
221          maxItems: 2
222
223  - if:
224      properties:
225        compatible:
226          contains:
227            enum:
228              - qcom,sm8650-cpufreq-epss
229    then:
230      properties:
231        reg:
232          minItems: 4
233          maxItems: 4
234
235        reg-names:
236          minItems: 4
237          maxItems: 4
238
239        interrupts:
240          minItems: 4
241          maxItems: 4
242
243        interrupt-names:
244          minItems: 4
245          maxItems: 4
246
247examples:
248  - |
249    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
250    #include <dt-bindings/clock/qcom,rpmh.h>
251
252    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
253    // switch DCVS state together.
254    cpus {
255      #address-cells = <2>;
256      #size-cells = <0>;
257
258      CPU0: cpu@0 {
259        device_type = "cpu";
260        compatible = "qcom,kryo385";
261        reg = <0x0 0x0>;
262        enable-method = "psci";
263        next-level-cache = <&L2_0>;
264        qcom,freq-domain = <&cpufreq_hw 0>;
265        clocks = <&cpufreq_hw 0>;
266        L2_0: l2-cache {
267          compatible = "cache";
268          cache-unified;
269          cache-level = <2>;
270          next-level-cache = <&L3_0>;
271          L3_0: l3-cache {
272            compatible = "cache";
273            cache-unified;
274            cache-level = <3>;
275          };
276        };
277      };
278
279      CPU1: cpu@100 {
280        device_type = "cpu";
281        compatible = "qcom,kryo385";
282        reg = <0x0 0x100>;
283        enable-method = "psci";
284        next-level-cache = <&L2_100>;
285        qcom,freq-domain = <&cpufreq_hw 0>;
286        clocks = <&cpufreq_hw 0>;
287        L2_100: l2-cache {
288          compatible = "cache";
289          cache-unified;
290          cache-level = <2>;
291          next-level-cache = <&L3_0>;
292        };
293      };
294
295      CPU2: cpu@200 {
296        device_type = "cpu";
297        compatible = "qcom,kryo385";
298        reg = <0x0 0x200>;
299        enable-method = "psci";
300        next-level-cache = <&L2_200>;
301        qcom,freq-domain = <&cpufreq_hw 0>;
302        clocks = <&cpufreq_hw 0>;
303        L2_200: l2-cache {
304          compatible = "cache";
305          cache-unified;
306          cache-level = <2>;
307          next-level-cache = <&L3_0>;
308        };
309      };
310
311      CPU3: cpu@300 {
312        device_type = "cpu";
313        compatible = "qcom,kryo385";
314        reg = <0x0 0x300>;
315        enable-method = "psci";
316        next-level-cache = <&L2_300>;
317        qcom,freq-domain = <&cpufreq_hw 0>;
318        clocks = <&cpufreq_hw 0>;
319        L2_300: l2-cache {
320          compatible = "cache";
321          cache-unified;
322          cache-level = <2>;
323          next-level-cache = <&L3_0>;
324        };
325      };
326
327      CPU4: cpu@400 {
328        device_type = "cpu";
329        compatible = "qcom,kryo385";
330        reg = <0x0 0x400>;
331        enable-method = "psci";
332        next-level-cache = <&L2_400>;
333        qcom,freq-domain = <&cpufreq_hw 1>;
334        clocks = <&cpufreq_hw 1>;
335        L2_400: l2-cache {
336          compatible = "cache";
337          cache-unified;
338          cache-level = <2>;
339          next-level-cache = <&L3_0>;
340        };
341      };
342
343      CPU5: cpu@500 {
344        device_type = "cpu";
345        compatible = "qcom,kryo385";
346        reg = <0x0 0x500>;
347        enable-method = "psci";
348        next-level-cache = <&L2_500>;
349        qcom,freq-domain = <&cpufreq_hw 1>;
350        clocks = <&cpufreq_hw 1>;
351        L2_500: l2-cache {
352          compatible = "cache";
353          cache-unified;
354          cache-level = <2>;
355          next-level-cache = <&L3_0>;
356        };
357      };
358
359      CPU6: cpu@600 {
360        device_type = "cpu";
361        compatible = "qcom,kryo385";
362        reg = <0x0 0x600>;
363        enable-method = "psci";
364        next-level-cache = <&L2_600>;
365        qcom,freq-domain = <&cpufreq_hw 1>;
366        clocks = <&cpufreq_hw 1>;
367        L2_600: l2-cache {
368          compatible = "cache";
369          cache-unified;
370          cache-level = <2>;
371          next-level-cache = <&L3_0>;
372        };
373      };
374
375      CPU7: cpu@700 {
376        device_type = "cpu";
377        compatible = "qcom,kryo385";
378        reg = <0x0 0x700>;
379        enable-method = "psci";
380        next-level-cache = <&L2_700>;
381        qcom,freq-domain = <&cpufreq_hw 1>;
382        clocks = <&cpufreq_hw 1>;
383        L2_700: l2-cache {
384          compatible = "cache";
385          cache-unified;
386          cache-level = <2>;
387          next-level-cache = <&L3_0>;
388        };
389      };
390    };
391
392    soc {
393      #address-cells = <1>;
394      #size-cells = <1>;
395
396      cpufreq@17d43000 {
397        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
398        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
399        reg-names = "freq-domain0", "freq-domain1";
400
401        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
402        clock-names = "xo", "alternate";
403
404        #freq-domain-cells = <1>;
405        #clock-cells = <1>;
406      };
407    };
408...
409