xref: /linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml (revision 68a052239fc4b351e961f698b824f7654a346091) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,qcs615-cpufreq-hw
26              - qcom,sc7180-cpufreq-hw
27              - qcom,sc8180x-cpufreq-hw
28              - qcom,sdm670-cpufreq-hw
29              - qcom,sdm845-cpufreq-hw
30              - qcom,sm6115-cpufreq-hw
31              - qcom,sm6350-cpufreq-hw
32              - qcom,sm8150-cpufreq-hw
33          - const: qcom,cpufreq-hw
34
35      - description: v2 of CPUFREQ HW (EPSS)
36        items:
37          - enum:
38              - qcom,qcs8300-cpufreq-epss
39              - qcom,qdu1000-cpufreq-epss
40              - qcom,sa8255p-cpufreq-epss
41              - qcom,sa8775p-cpufreq-epss
42              - qcom,sar2130p-cpufreq-epss
43              - qcom,sc7280-cpufreq-epss
44              - qcom,sc8280xp-cpufreq-epss
45              - qcom,sdx75-cpufreq-epss
46              - qcom,sm4450-cpufreq-epss
47              - qcom,sm6375-cpufreq-epss
48              - qcom,sm8250-cpufreq-epss
49              - qcom,sm8350-cpufreq-epss
50              - qcom,sm8450-cpufreq-epss
51              - qcom,sm8550-cpufreq-epss
52              - qcom,sm8650-cpufreq-epss
53          - const: qcom,cpufreq-epss
54
55  reg:
56    minItems: 1
57    items:
58      - description: Frequency domain 0 register region
59      - description: Frequency domain 1 register region
60      - description: Frequency domain 2 register region
61      - description: Frequency domain 3 register region
62
63  reg-names:
64    minItems: 1
65    items:
66      - const: freq-domain0
67      - const: freq-domain1
68      - const: freq-domain2
69      - const: freq-domain3
70
71  clocks:
72    items:
73      - description: XO Clock
74      - description: GPLL0 Clock
75
76  clock-names:
77    items:
78      - const: xo
79      - const: alternate
80
81  interrupts:
82    minItems: 1
83    maxItems: 4
84
85  interrupt-names:
86    minItems: 1
87    items:
88      - const: dcvsh-irq-0
89      - const: dcvsh-irq-1
90      - const: dcvsh-irq-2
91      - const: dcvsh-irq-3
92
93  '#freq-domain-cells':
94    const: 1
95
96  '#clock-cells':
97    const: 1
98
99required:
100  - compatible
101  - reg
102  - clocks
103  - clock-names
104  - '#freq-domain-cells'
105
106additionalProperties: false
107
108allOf:
109  - if:
110      properties:
111        compatible:
112          contains:
113            enum:
114              - qcom,qcm2290-cpufreq-hw
115              - qcom,sar2130p-cpufreq-epss
116              - qcom,sdx75-cpufreq-epss
117    then:
118      properties:
119        reg:
120          maxItems: 1
121
122        reg-names:
123          maxItems: 1
124
125        interrupts:
126          maxItems: 1
127
128        interrupt-names:
129          maxItems: 1
130
131  - if:
132      properties:
133        compatible:
134          contains:
135            enum:
136              - qcom,qcs615-cpufreq-hw
137              - qcom,qdu1000-cpufreq-epss
138              - qcom,sa8255p-cpufreq-epss
139              - qcom,sa8775p-cpufreq-epss
140              - qcom,sc7180-cpufreq-hw
141              - qcom,sc8180x-cpufreq-hw
142              - qcom,sc8280xp-cpufreq-epss
143              - qcom,sdm670-cpufreq-hw
144              - qcom,sdm845-cpufreq-hw
145              - qcom,sm4450-cpufreq-epss
146              - qcom,sm6115-cpufreq-hw
147              - qcom,sm6350-cpufreq-hw
148              - qcom,sm6375-cpufreq-epss
149    then:
150      properties:
151        reg:
152          minItems: 2
153          maxItems: 2
154
155        reg-names:
156          minItems: 2
157          maxItems: 2
158
159        interrupts:
160          minItems: 2
161          maxItems: 2
162
163        interrupt-names:
164          minItems: 2
165          maxItems: 2
166
167  - if:
168      properties:
169        compatible:
170          contains:
171            enum:
172              - qcom,qcs8300-cpufreq-epss
173              - qcom,sc7280-cpufreq-epss
174              - qcom,sm8250-cpufreq-epss
175              - qcom,sm8350-cpufreq-epss
176              - qcom,sm8450-cpufreq-epss
177              - qcom,sm8550-cpufreq-epss
178    then:
179      properties:
180        reg:
181          minItems: 3
182          maxItems: 3
183
184        reg-names:
185          minItems: 3
186          maxItems: 3
187
188        interrupts:
189          minItems: 3
190          maxItems: 3
191
192        interrupt-names:
193          minItems: 3
194          maxItems: 3
195
196  - if:
197      properties:
198        compatible:
199          contains:
200            enum:
201              - qcom,sm8150-cpufreq-hw
202    then:
203      properties:
204        reg:
205          minItems: 3
206          maxItems: 3
207
208        reg-names:
209          minItems: 3
210          maxItems: 3
211
212        # On some SoCs the Prime core shares the LMH irq with Big cores
213        interrupts:
214          minItems: 2
215          maxItems: 2
216
217        interrupt-names:
218          minItems: 2
219          maxItems: 2
220
221  - if:
222      properties:
223        compatible:
224          contains:
225            enum:
226              - qcom,sm8650-cpufreq-epss
227    then:
228      properties:
229        reg:
230          minItems: 4
231          maxItems: 4
232
233        reg-names:
234          minItems: 4
235          maxItems: 4
236
237        interrupts:
238          minItems: 4
239          maxItems: 4
240
241        interrupt-names:
242          minItems: 4
243          maxItems: 4
244
245examples:
246  - |
247    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
248    #include <dt-bindings/clock/qcom,rpmh.h>
249
250    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
251    // switch DCVS state together.
252    cpus {
253      #address-cells = <2>;
254      #size-cells = <0>;
255
256      CPU0: cpu@0 {
257        device_type = "cpu";
258        compatible = "qcom,kryo385";
259        reg = <0x0 0x0>;
260        enable-method = "psci";
261        next-level-cache = <&L2_0>;
262        qcom,freq-domain = <&cpufreq_hw 0>;
263        clocks = <&cpufreq_hw 0>;
264        L2_0: l2-cache {
265          compatible = "cache";
266          cache-unified;
267          cache-level = <2>;
268          next-level-cache = <&L3_0>;
269          L3_0: l3-cache {
270            compatible = "cache";
271            cache-unified;
272            cache-level = <3>;
273          };
274        };
275      };
276
277      CPU1: cpu@100 {
278        device_type = "cpu";
279        compatible = "qcom,kryo385";
280        reg = <0x0 0x100>;
281        enable-method = "psci";
282        next-level-cache = <&L2_100>;
283        qcom,freq-domain = <&cpufreq_hw 0>;
284        clocks = <&cpufreq_hw 0>;
285        L2_100: l2-cache {
286          compatible = "cache";
287          cache-unified;
288          cache-level = <2>;
289          next-level-cache = <&L3_0>;
290        };
291      };
292
293      CPU2: cpu@200 {
294        device_type = "cpu";
295        compatible = "qcom,kryo385";
296        reg = <0x0 0x200>;
297        enable-method = "psci";
298        next-level-cache = <&L2_200>;
299        qcom,freq-domain = <&cpufreq_hw 0>;
300        clocks = <&cpufreq_hw 0>;
301        L2_200: l2-cache {
302          compatible = "cache";
303          cache-unified;
304          cache-level = <2>;
305          next-level-cache = <&L3_0>;
306        };
307      };
308
309      CPU3: cpu@300 {
310        device_type = "cpu";
311        compatible = "qcom,kryo385";
312        reg = <0x0 0x300>;
313        enable-method = "psci";
314        next-level-cache = <&L2_300>;
315        qcom,freq-domain = <&cpufreq_hw 0>;
316        clocks = <&cpufreq_hw 0>;
317        L2_300: l2-cache {
318          compatible = "cache";
319          cache-unified;
320          cache-level = <2>;
321          next-level-cache = <&L3_0>;
322        };
323      };
324
325      CPU4: cpu@400 {
326        device_type = "cpu";
327        compatible = "qcom,kryo385";
328        reg = <0x0 0x400>;
329        enable-method = "psci";
330        next-level-cache = <&L2_400>;
331        qcom,freq-domain = <&cpufreq_hw 1>;
332        clocks = <&cpufreq_hw 1>;
333        L2_400: l2-cache {
334          compatible = "cache";
335          cache-unified;
336          cache-level = <2>;
337          next-level-cache = <&L3_0>;
338        };
339      };
340
341      CPU5: cpu@500 {
342        device_type = "cpu";
343        compatible = "qcom,kryo385";
344        reg = <0x0 0x500>;
345        enable-method = "psci";
346        next-level-cache = <&L2_500>;
347        qcom,freq-domain = <&cpufreq_hw 1>;
348        clocks = <&cpufreq_hw 1>;
349        L2_500: l2-cache {
350          compatible = "cache";
351          cache-unified;
352          cache-level = <2>;
353          next-level-cache = <&L3_0>;
354        };
355      };
356
357      CPU6: cpu@600 {
358        device_type = "cpu";
359        compatible = "qcom,kryo385";
360        reg = <0x0 0x600>;
361        enable-method = "psci";
362        next-level-cache = <&L2_600>;
363        qcom,freq-domain = <&cpufreq_hw 1>;
364        clocks = <&cpufreq_hw 1>;
365        L2_600: l2-cache {
366          compatible = "cache";
367          cache-unified;
368          cache-level = <2>;
369          next-level-cache = <&L3_0>;
370        };
371      };
372
373      CPU7: cpu@700 {
374        device_type = "cpu";
375        compatible = "qcom,kryo385";
376        reg = <0x0 0x700>;
377        enable-method = "psci";
378        next-level-cache = <&L2_700>;
379        qcom,freq-domain = <&cpufreq_hw 1>;
380        clocks = <&cpufreq_hw 1>;
381        L2_700: l2-cache {
382          compatible = "cache";
383          cache-unified;
384          cache-level = <2>;
385          next-level-cache = <&L3_0>;
386        };
387      };
388    };
389
390    soc {
391      #address-cells = <1>;
392      #size-cells = <1>;
393
394      cpufreq@17d43000 {
395        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
396        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
397        reg-names = "freq-domain0", "freq-domain1";
398
399        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
400        clock-names = "xo", "alternate";
401
402        #freq-domain-cells = <1>;
403        #clock-cells = <1>;
404      };
405    };
406...
407