xref: /linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,qcs615-cpufreq-hw
26              - qcom,sc7180-cpufreq-hw
27              - qcom,sc8180x-cpufreq-hw
28              - qcom,sdm670-cpufreq-hw
29              - qcom,sdm845-cpufreq-hw
30              - qcom,sm6115-cpufreq-hw
31              - qcom,sm6350-cpufreq-hw
32              - qcom,sm8150-cpufreq-hw
33          - const: qcom,cpufreq-hw
34
35      - description: v2 of CPUFREQ HW (EPSS)
36        items:
37          - enum:
38              - qcom,eliza-cpufreq-epss
39              - qcom,milos-cpufreq-epss
40              - qcom,qcs8300-cpufreq-epss
41              - qcom,qdu1000-cpufreq-epss
42              - qcom,sa8255p-cpufreq-epss
43              - qcom,sa8775p-cpufreq-epss
44              - qcom,sar2130p-cpufreq-epss
45              - qcom,sc7280-cpufreq-epss
46              - qcom,sc8280xp-cpufreq-epss
47              - qcom,sdx75-cpufreq-epss
48              - qcom,sm4450-cpufreq-epss
49              - qcom,sm6375-cpufreq-epss
50              - qcom,sm8250-cpufreq-epss
51              - qcom,sm8350-cpufreq-epss
52              - qcom,sm8450-cpufreq-epss
53              - qcom,sm8550-cpufreq-epss
54              - qcom,sm8650-cpufreq-epss
55          - const: qcom,cpufreq-epss
56
57  reg:
58    minItems: 1
59    items:
60      - description: Frequency domain 0 register region
61      - description: Frequency domain 1 register region
62      - description: Frequency domain 2 register region
63      - description: Frequency domain 3 register region
64
65  reg-names:
66    minItems: 1
67    items:
68      - const: freq-domain0
69      - const: freq-domain1
70      - const: freq-domain2
71      - const: freq-domain3
72
73  clocks:
74    items:
75      - description: XO Clock
76      - description: GPLL0 Clock
77
78  clock-names:
79    items:
80      - const: xo
81      - const: alternate
82
83  interrupts:
84    minItems: 1
85    maxItems: 4
86
87  interrupt-names:
88    minItems: 1
89    items:
90      - const: dcvsh-irq-0
91      - const: dcvsh-irq-1
92      - const: dcvsh-irq-2
93      - const: dcvsh-irq-3
94
95  '#freq-domain-cells':
96    const: 1
97
98  '#clock-cells':
99    const: 1
100
101required:
102  - compatible
103  - reg
104  - clocks
105  - clock-names
106  - '#freq-domain-cells'
107
108additionalProperties: false
109
110allOf:
111  - if:
112      properties:
113        compatible:
114          contains:
115            enum:
116              - qcom,qcm2290-cpufreq-hw
117              - qcom,sar2130p-cpufreq-epss
118              - qcom,sdx75-cpufreq-epss
119    then:
120      properties:
121        reg:
122          maxItems: 1
123
124        reg-names:
125          maxItems: 1
126
127        interrupts:
128          maxItems: 1
129
130        interrupt-names:
131          maxItems: 1
132
133  - if:
134      properties:
135        compatible:
136          contains:
137            enum:
138              - qcom,qcs615-cpufreq-hw
139              - qcom,qdu1000-cpufreq-epss
140              - qcom,sa8255p-cpufreq-epss
141              - qcom,sa8775p-cpufreq-epss
142              - qcom,sc7180-cpufreq-hw
143              - qcom,sc8180x-cpufreq-hw
144              - qcom,sc8280xp-cpufreq-epss
145              - qcom,sdm670-cpufreq-hw
146              - qcom,sdm845-cpufreq-hw
147              - qcom,sm4450-cpufreq-epss
148              - qcom,sm6115-cpufreq-hw
149              - qcom,sm6350-cpufreq-hw
150              - qcom,sm6375-cpufreq-epss
151    then:
152      properties:
153        reg:
154          minItems: 2
155          maxItems: 2
156
157        reg-names:
158          minItems: 2
159          maxItems: 2
160
161        interrupts:
162          minItems: 2
163          maxItems: 2
164
165        interrupt-names:
166          minItems: 2
167          maxItems: 2
168
169  - if:
170      properties:
171        compatible:
172          contains:
173            enum:
174              - qcom,milos-cpufreq-epss
175              - qcom,qcs8300-cpufreq-epss
176              - qcom,sc7280-cpufreq-epss
177              - qcom,sm8250-cpufreq-epss
178              - qcom,sm8350-cpufreq-epss
179              - qcom,sm8450-cpufreq-epss
180              - qcom,sm8550-cpufreq-epss
181    then:
182      properties:
183        reg:
184          minItems: 3
185          maxItems: 3
186
187        reg-names:
188          minItems: 3
189          maxItems: 3
190
191        interrupts:
192          minItems: 3
193          maxItems: 3
194
195        interrupt-names:
196          minItems: 3
197          maxItems: 3
198
199  - if:
200      properties:
201        compatible:
202          contains:
203            enum:
204              - qcom,sm8150-cpufreq-hw
205    then:
206      properties:
207        reg:
208          minItems: 3
209          maxItems: 3
210
211        reg-names:
212          minItems: 3
213          maxItems: 3
214
215        # On some SoCs the Prime core shares the LMH irq with Big cores
216        interrupts:
217          minItems: 2
218          maxItems: 2
219
220        interrupt-names:
221          minItems: 2
222          maxItems: 2
223
224  - if:
225      properties:
226        compatible:
227          contains:
228            enum:
229              - qcom,sm8650-cpufreq-epss
230    then:
231      properties:
232        reg:
233          minItems: 4
234          maxItems: 4
235
236        reg-names:
237          minItems: 4
238          maxItems: 4
239
240        interrupts:
241          minItems: 4
242          maxItems: 4
243
244        interrupt-names:
245          minItems: 4
246          maxItems: 4
247
248examples:
249  - |
250    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
251    #include <dt-bindings/clock/qcom,rpmh.h>
252
253    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
254    // switch DCVS state together.
255    cpus {
256      #address-cells = <2>;
257      #size-cells = <0>;
258
259      CPU0: cpu@0 {
260        device_type = "cpu";
261        compatible = "qcom,kryo385";
262        reg = <0x0 0x0>;
263        enable-method = "psci";
264        next-level-cache = <&L2_0>;
265        qcom,freq-domain = <&cpufreq_hw 0>;
266        clocks = <&cpufreq_hw 0>;
267        L2_0: l2-cache {
268          compatible = "cache";
269          cache-unified;
270          cache-level = <2>;
271          next-level-cache = <&L3_0>;
272          L3_0: l3-cache {
273            compatible = "cache";
274            cache-unified;
275            cache-level = <3>;
276          };
277        };
278      };
279
280      CPU1: cpu@100 {
281        device_type = "cpu";
282        compatible = "qcom,kryo385";
283        reg = <0x0 0x100>;
284        enable-method = "psci";
285        next-level-cache = <&L2_100>;
286        qcom,freq-domain = <&cpufreq_hw 0>;
287        clocks = <&cpufreq_hw 0>;
288        L2_100: l2-cache {
289          compatible = "cache";
290          cache-unified;
291          cache-level = <2>;
292          next-level-cache = <&L3_0>;
293        };
294      };
295
296      CPU2: cpu@200 {
297        device_type = "cpu";
298        compatible = "qcom,kryo385";
299        reg = <0x0 0x200>;
300        enable-method = "psci";
301        next-level-cache = <&L2_200>;
302        qcom,freq-domain = <&cpufreq_hw 0>;
303        clocks = <&cpufreq_hw 0>;
304        L2_200: l2-cache {
305          compatible = "cache";
306          cache-unified;
307          cache-level = <2>;
308          next-level-cache = <&L3_0>;
309        };
310      };
311
312      CPU3: cpu@300 {
313        device_type = "cpu";
314        compatible = "qcom,kryo385";
315        reg = <0x0 0x300>;
316        enable-method = "psci";
317        next-level-cache = <&L2_300>;
318        qcom,freq-domain = <&cpufreq_hw 0>;
319        clocks = <&cpufreq_hw 0>;
320        L2_300: l2-cache {
321          compatible = "cache";
322          cache-unified;
323          cache-level = <2>;
324          next-level-cache = <&L3_0>;
325        };
326      };
327
328      CPU4: cpu@400 {
329        device_type = "cpu";
330        compatible = "qcom,kryo385";
331        reg = <0x0 0x400>;
332        enable-method = "psci";
333        next-level-cache = <&L2_400>;
334        qcom,freq-domain = <&cpufreq_hw 1>;
335        clocks = <&cpufreq_hw 1>;
336        L2_400: l2-cache {
337          compatible = "cache";
338          cache-unified;
339          cache-level = <2>;
340          next-level-cache = <&L3_0>;
341        };
342      };
343
344      CPU5: cpu@500 {
345        device_type = "cpu";
346        compatible = "qcom,kryo385";
347        reg = <0x0 0x500>;
348        enable-method = "psci";
349        next-level-cache = <&L2_500>;
350        qcom,freq-domain = <&cpufreq_hw 1>;
351        clocks = <&cpufreq_hw 1>;
352        L2_500: l2-cache {
353          compatible = "cache";
354          cache-unified;
355          cache-level = <2>;
356          next-level-cache = <&L3_0>;
357        };
358      };
359
360      CPU6: cpu@600 {
361        device_type = "cpu";
362        compatible = "qcom,kryo385";
363        reg = <0x0 0x600>;
364        enable-method = "psci";
365        next-level-cache = <&L2_600>;
366        qcom,freq-domain = <&cpufreq_hw 1>;
367        clocks = <&cpufreq_hw 1>;
368        L2_600: l2-cache {
369          compatible = "cache";
370          cache-unified;
371          cache-level = <2>;
372          next-level-cache = <&L3_0>;
373        };
374      };
375
376      CPU7: cpu@700 {
377        device_type = "cpu";
378        compatible = "qcom,kryo385";
379        reg = <0x0 0x700>;
380        enable-method = "psci";
381        next-level-cache = <&L2_700>;
382        qcom,freq-domain = <&cpufreq_hw 1>;
383        clocks = <&cpufreq_hw 1>;
384        L2_700: l2-cache {
385          compatible = "cache";
386          cache-unified;
387          cache-level = <2>;
388          next-level-cache = <&L3_0>;
389        };
390      };
391    };
392
393    soc {
394      #address-cells = <1>;
395      #size-cells = <1>;
396
397      cpufreq@17d43000 {
398        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
399        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
400        reg-names = "freq-domain0", "freq-domain1";
401
402        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
403        clock-names = "xo", "alternate";
404
405        #freq-domain-cells = <1>;
406        #clock-cells = <1>;
407      };
408    };
409...
410